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A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

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Abstract

This paper presents the design and Silicon verification of a 2.488–11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps.

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Acknowledgments

The authors would like to acknowledge the support of the lab teams from MoSys and **linx for help with the silicon measurements.

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Authors and Affiliations

  1. MoSys Inc., Santa Clara, CA, 95054, USA

    Socrates D. Vamvakos, Claude R. Gauthier, Chethan Rao, Alvin Wang, Karthisha Ramoshan Canagasaby, Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, K. C. Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf & Jason Yeung

  2. **linx Inc., San Jose, CA, 95124, USA

    Khaldoon Abugharbieh & Ying Cao

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  1. Socrates D. Vamvakos
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  2. Claude R. Gauthier
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  3. Chethan Rao
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  5. Karthisha Ramoshan Canagasaby
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  12. Bendik Kleveland
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  13. Gurupada Mandal
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  15. Ritesh Saraf
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  16. Jason Yeung
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  17. Ying Cao
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Correspondence to Socrates D. Vamvakos.

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Vamvakos, S.D., Gauthier, C.R., Rao, C. et al. A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications. Analog Integr Circ Sig Process 78, 259–273 (2014). https://doi.org/10.1007/s10470-013-0172-1

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  • DOI: https://doi.org/10.1007/s10470-013-0172-1

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