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Efficient chip-shape correlator implementation on a GPU-based real-time GNSS SDR receiver

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Abstract

Global navigation satellite system (GNSS) software-defined radio (SDR) receivers play a very important role in many fields of GNSS due to their flexibility and configurability. In an SDR receiver, the correlation process is the main computational burden. Correlation acceleration based on a graphics processing unit (GPU) meets the real-time requirements of a modern SDR receiver. The chip-shape correlator based on signal compression can effectively measure the correlation function and chip shape, which is necessary for some multipath mitigation and signal quality monitoring algorithms. We present a GPU-based chip-shape correlator architecture implemented with CUDA, in which the chip transitions and multiple correlator values can be calculated by signal compression. Especially for the parallel algorithm of signal compression, a sample-to-thread map** mechanism is further proposed to greatly reduce registers used per thread, which can avoid register spilling and improve performance. The test results show that while processing the 84 channels of 7 signals at the same time, our SDR receiver with the designed chip-shape correlator based on a GPU can complete chip shape transition measurement and calculation of 39 correlator values of 1 ms GNSS data within 0.6 ms, meeting the real-time processing requirement.

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Appendix: example of \({\mathbf{P}}_{\mathbf{i}}\) calculation

Appendix: example of \({\mathbf{P}}_{\mathbf{i}}\) calculation

To better explain the calculation method of \({\mathrm{P}}_{\mathrm{i}}\), an example of \({\mathrm{N}}_{b}=40\), \({\mathrm{f}}_{\mathrm{s}}\)=24 MHz and \({\mathrm{f}}_{\mathrm{c}}\)=1.023 MHz is given to show the process of calculating and determining \({\mathrm{P}}_{\mathrm{i}}\)

Substitute the above values of \({\mathrm{N}}_{b}, {\mathrm{f}}_{\mathrm{s}}\) and \({\mathrm{f}}_{\mathrm{c}}\) into (12)

$$\begin{array}{c}\frac{40\mathrm{k}-1}{1.705}<{\mathrm{n}}_{2}-{\mathrm{n}}_{1}<\frac{40\mathrm{k}+1}{1.705},k\in {\mathrm{N}}^{+}\end{array}$$
(16)

Therefore, when k \(=1\)

$$\begin{array}{c}22.87=\frac{39}{1.705}<{\mathrm{n}}_{2}-{\mathrm{n}}_{1}<\frac{41}{1.705}=24.05\end{array}$$
(17)
$$\begin{array}{c}{\mathrm{n}}_{2}-{\mathrm{n}}_{1}=\mathrm{23,24}\end{array}$$
(18)

When \(k=2\)

$$\begin{array}{c}46.33=\frac{79}{1.705}<{\mathrm{n}}_{2}-{\mathrm{n}}_{1}<\frac{81}{1.705}=47.51\end{array}$$
(19)
$$\begin{array}{c}{\mathrm{n}}_{2}-{\mathrm{n}}_{1}=47\end{array}$$
(20)

Therefore, \({\mathrm{Q}}_{1}=23,{\mathrm{Q}}_{2}=24,{\mathrm{Q}}_{3}=47\) are the smallest three possible intervals between two samples that fall in the same bin.

Substituting \({\mathrm{Q}}_{1}=23,{\mathrm{Q}}_{2}=24,{\mathrm{Q}}_{3}=47\) into (13) to get,

$$\begin{array}{c}{\mathrm{A}}_{1}=-0.785,{\mathrm{A}}_{2}=0.92,{\mathrm{A}}_{3}=0.135\end{array}$$
(21)

From (14),

$$\begin{array}{c}{\mathrm{F}}_{1}\in \left[\mathrm{0.785,1}\right),{\mathrm{F}}_{2}\in \left[\mathrm{0,0.08}\right),{\mathrm{F}}_{3}\in \left[\mathrm{0,0.865}\right)\end{array}$$
(22)

can be obtained.

$$\begin{array}{c}\left[\mathrm{0.785,1}\right)\cup \left[\mathrm{0,0.08}\right)\cup \left[\mathrm{0,0.865}\right)=\left[\mathrm{0,1}\right)\end{array}$$
(23)

Therefore, there are only \({\mathrm{P}}_{1}=23,{\mathrm{P}}_{2}=24,{\mathrm{P}}_{3}=47\) for the values of \({\mathrm{P}}_{\mathrm{i}}\).

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Wang, C., Wang, X., Cui, X. et al. Efficient chip-shape correlator implementation on a GPU-based real-time GNSS SDR receiver. GPS Solut 26, 143 (2022). https://doi.org/10.1007/s10291-022-01332-1

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