1 Introduction

As Moore’s Law continues to evolve, the pursuit of faster switching speeds, lower power consumption, and smaller size variations has driven transistor technology through successive generations, transitioning from traditional planar transistor (Planar FET), nanowire, FinFET, to nanosheet. Among these advancements, nanosheets exhibit remarkable design flexibility, allowing the channel width to increase for enhanced current flow or decrease to limit power consumption. Stacked nanosheet transistors have been confirmed as the primary component structure for 3 nm technology nodes and smaller advanced technologies. Compared to FinFET, they demonstrate superior electrostatic characteristics and short channel control, making them the mainstream application for TSMC and Samsung in the 3 nm structure [1, 2].

However, Nanosheets also bring along significant challenges, such as the trade-offs between transistor switching speed, power consumption, process complexity, and cost. This trade-off is closely related to the channel width, commonly referred to as Weff. Larger widths imply the ability to drive more current, facilitating quicker transistor on–off transitions, but they also necessitate a more complex and expensive manufacturing process [3].

Despite Nanosheets becoming the mainstream application for TSMC and Samsung in the 3 nm architecture, MOSFETs still face challenges in overcoming the thermal limitation (thermal constraint) of 60 mV/decade SS at room temperature (300 K) and the difficulty in reducing the power supply voltage (VD) below 0.5 V [4]. As the Internet of Things (IoT) and artificial intelligence (AI) chip technologies rapidly advance, the increasing demand for higher voltages becomes an undeniable challenge for future device power consumption.

In response to this, researchers propose Tunnel Field-Effect Transistor (TFET) that leverage their Band-to-Band quantum tunneling mechanism to overcome carrier Boltzmann distribution. These devices, in comparison to Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs), offer advantages, enabling high performance under extremely low operating bias conditions, achieving low power consumption and rapid switching effects [5, 6].

Normally, Tunnel Field-Effect Transistor (TFET) exhibits two tunneling current generation mechanisms [7]. The first is “point tunneling”, occurring at the source-channel interface, with its primary contribution confined to a small region. Due to the limited tunneling area, the Band-to-Band effect is restricted, resulting in a Subthreshold Swing (SS) that does not reach an ideal level. The second is “line tunneling”, located in the source region overlap** with the gate. As the region where Band to Band begins resembles a line, this component is referred to as “line tunneling”. Compared to point tunneling, line tunneling has a broader tunneling area, and the current is directly proportional to both the channel width (W) and channel length (L) of the device, effectively improving subthreshold swing (SS) [8,9,10,11,12,13,14]. In this work, we will discuss and compare the results obtained from these two tunneling mechanisms.

We have also made improvements in addressing the expensive manufacturing processes by adopting a SiGe (70% Si and 30% Ge) monolithic material for stacking. The source metal is configured as a Schottky contact, forming different Schottky barrier heights by utilizing metals with distinct work functions. This leads to the inversion of a thinner carrier inversion layer, replacing the need for do** and thermal annealing associated with traditional material stacking. Simultaneously, this approach expands the area on the source side, thereby increasing the linear tunneling area between the gate and source, further enhancing the device’s performance [5].

Our proposed iTFET utilizes Schottky contacts to achieve a total line-tunneling dominated TFET. In contrast to traditional TFETs that require do** to establish p-type and n-type regions for P–I–N or P–N–N structures, iTFETs use a single piece of N-substrate with uniform do** concentration. Due to the band bending, thermal activation creates an inversion layer, converting the Source region into P-type, thus forming an overall PN structure [15].

In Sect. 2, we will present the device design, manufacturing steps, and simulation methods. In Sect. 3 will discuss the circuit characteristics under various parameter variations and simulation results. Finally, Sect. 4 will summarize the conclusions of this study.

2 Device design and simulation method

We conducted a comparison of Nanosheet PIN TFET, Nanosheet iTFET, and Fin iTFET with body thicknesses of 5 nm and 3 nm. Figure 1 shows the SiGe Body thickness of 5 nm for Nanosheet PIN TFET, Nanosheet iTFET, and FinFET iTFET. In Fig. 2, the SiGe Body thickness is depicted as 3 nm.

Fig. 1
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SiGe Body thickness is 5 nm of a Nanosheet PIN TFET. b Nanosheet iTFET. c Fin iTFET

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Fig. 2
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SiGe Body thickness is 3 nm of a Nanosheet PIN TFET. b Nanosheet iTFET. c Fin iTFET

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Figure 3 shows the cross-sectional diagrams of the Nanosheet PIN TFET and Nanosheet iTFET. Various device parameters are presented in Table 1. By replacing traditional Si with SiGe, having a carrier mobility three times that of Si, we achieved superior Band-to-Band characteristics [16]. A PN junction can be formed by utilizing the Schottky contact characteristics of a metal–semiconductor contact with different work functions. To enhance the reliability of the comparison, we employed a uniform overall structure with dimensions of 55 × 25 × 55 (nm3) and 55 × 33 × 33 (nm3) for length, width, and height, respectively. Although the gate channel length of Nanosheet PIN TFET is 35 nm, the same as the other two, the presence of additional do** regions increased its length by 20 nm, resulting in overall dimensions of 75 × 25 × 55 (nm3) and 75 × 33 × 33 (nm3). This is a drawback of Nanosheet PIN TFET, requiring a larger volume and incurring higher process costs.

Fig. 3
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This is a cross-sectional diagram of a Nanosheet PIN TFET. b Nanosheet iTFET

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Table 1 The SiGe Body thickness is 5 nm/3 nm for device parameters
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Even with efforts to use the same lengths for reliable device comparison, unavoidable adjustments may arise, such as when the body thickness is adjusted from 5 to 3 nm. Considering process-related factors, the gate oxide thickness (tox) must also be adjusted with the change in body thickness. Furthermore, in Nanosheet iTFET and Fin iTFET, we employed a uniform do** concentration. In contrast, Nanosheet PIN TFET requires different do** concentrations at various locations to achieve the desired device characteristics. When selecting do** concentrations, we specifically considered the optimal characteristics for each device. Specifically, the do** concentration for Nanosheet iTFET and Fin iTFET is uniformly set at 1 × 1018 cm−3. Meanwhile, for Nanosheet PIN TFET, the P-type do** concentration is 1 × 1020 cm−3, the I-type do** concentration is 1 × 1016 cm−3, and the N-type do** concentration is 1 × 1018 cm−3. In Sect. 3 we will provide a more detailed description of the optimization of device parameters.

In this paper, we employed Sentaurus TCAD to simulate the electrical characteristics of three different types of Tunnel Field-Effect Transistor (TFET) structures proposed by us under various parameter variations. To accurately calculate tunneling currents, we adopted the Dynamic Nonlocal Path Band-to-Band Tunneling Model. Additionally, we accounted for device non-ideal effects, incorporating the Shockley–Read–Hall recombination (SRH) model, Bandgap narrowing, High-field saturation mobility models, Auger recombination model, and considering minute fabrication details, we introduced quantum confinement effects. To ensure the accuracy and feasibility of the simulations, we utilized experimentally fabricated Si/SiGe heterojunctions, considering TFETs that exhibit both line and point tunneling simultaneously [5]. Model calibration for the simulations is illustrated in Fig. 4.

Fig. 4
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TCAD model calibration using experimental data [17]

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The fabrication process for the stacked SiGe nanosheet iTFET is shown in Fig. 5. To begin, multi-layer SiGe/Si/Ge stacks, each with 5 nm Ge0.3Si0.7 and 5 nm Si, were grown in a reduced-pressure chemical vapor deposition (RPVVD) chamber in Fig. 5a. Following the stack growth, fin arrays patterns were precisely created utilizing the spacer image transfer (SIT) technique, achieving a resolution beyond that of advanced photolithography. This meticulous method guaranteed the accurate definition of the intended fin structures in Fig. 5b. To define the fins, fin etching was performed, sha**, refining the structures to the required specifications in Fig. 5c. Shallow trench isolation (STI) was introduced, while a SiO2 with a high aspect ratio process (HARP) was deposited to enhance the overall structure, providing essential isolation for subsequent transistor components. To reveal the fin, diluted hydrofluoric acid (DHF) was used to perform a SiO2 etching process in Fig. 5d. A dummy gate stack was formed on the fins during the execution of dummy gate formation in Fig. 5(e). SiO2 spacers were carefully formed in Fig. 5f. S/D cavity etching and partial etching of Ge and Si were performed in Fig. 5g. A one-sided inner spacer was meticulously achieved by depositing a thin layer of SiNx and employing the Reactive Ion Etching (RIE) process in Fig. 5h. The Ge0.3Si0.7 epitaxy process with in-situ do** was followed by the epitaxial growth of the source and drain regions in Fig. 5i. ILD0 deposition was carried out in Fig. 5j. Dummy gate was promptly eliminated through immersion in tetramethylammonium hydroxide in Fig. 5k. The release of Ge Nanosheet (NS) channels through selective etching in Fig. 5l. Source metal deposition in Fig. 5m. Source metal partially removed in Fig. 5n. Selective etching released Si Nanosheet (NS) channels in Fig. 5o. The multilayer High-K Metal Gate (HKMG) film stacks were applied using an Atom Layer Deposition (ALD) method. In Fig. 5p. Chemical mechanical planarization (CMP) was applied, smoothing, and refining the device’s surface in Fig. 5q. ILD deposition was carried out in Fig. 5r. Finally, metal deposition and contact were established in Fig. 5s [24]. When the band bending reaches a certain degree, leakage current also starts to increase due to tunneling in the off state. It can be observed that when φb = 0.9, the tunneling effect on leakage current becomes more pronounced, resulting in a slightly higher IOFF compared to φb = 0.8. This suggests that an increase in φb does not necessarily lead to an absolute improvement in device performance in Fig. 19a, b.

Fig. 17
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ID–VG characteristic curves for different Schottky barrier heights of the Nanosheet iTFET

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Fig. 18
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ION/IOFF, SSavg, for different Schottky barrier heights of the Nanosheet iTFET

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Fig. 19
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a Band diagram, b Band-to-band generation for different Schottky barrier heights of the Nanosheet iTFET

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Figure 20 shows the current variation at different SiGe Body thicknesses. As the Nanosheet iTFET primarily adopts the line tunneling mechanism, a thinner substrate not only reduces the device’s volume but also shortens the tunneling distance between the Gate and Source, enhancing the Band-to-Band tunneling effect and thus improving device performance. Therefore, the choice of substrate thickness is crucial for TFET performance. We observe that when the SiGe Body thickness is 3 nm, it not only exhibits optimal ION/IOFF but also achieves the lowest SS and minimal volume. Conversely, when the SiGe Body thickness > 10 nm, the tunneling effect becomes less favorable, leading to an SS exceeding 60 mV/dec, which compromises the TFET’s advantage in rapid switching compared to MOSFET in Fig. 21.

Fig. 20
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ID–VG characteristic curves for different SiGe body thickness of the Nanosheet iTFET

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Fig. 21
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ION/IOFF, SSavg, for different SiGe body thickness of the Nanosheet iTFET

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3.3 The non-ideal effects of the device and improvement

The presence of interface traps has been observed to reduce the conduction current in tunneling TFETs, primarily relying on the tunneling interface lateral electric field peak. Since interface traps are only present on the interface at channel-drain tunneling junction only, the on-current is likely unaffected by interface traps. However, the ambipolar conduction induced by the motion of charged carriers at the output tunneling interface is significantly influenced by interface traps. It can be noted that both points tunneling-dominated PIN TFET and line tunneling-dominated Nanosheet iTFET are affected by traps, as illustrated in Fig. 22a–c. To mitigate the impact of traps on device performance, apart from employing High-K materials proposed by others in this device, we have suggested several methods to ameliorate the effects of traps [25,26,27].

Fig. 22
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a ID–VG characteristic curves of the PIN TFET, b of the Nanosheet iTFET, c of the Fin iTFET for different interface trap densities

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Since interface traps typically occur at the interface between HfO2 and SiGe Body, with the increase in interface trap density, the negative charge density at the interface increases, thereby increasing the electron concentration at the interface. This situation induces band bending in the interface tunneling oxide. The introduction of traps creates new tunneling channels for charge carriers to cross the bandgap, resulting in leakage current occurring even in the off state due to tunneling. Therefore, the occurrence of tunneling phenomena leads to an increasing trend in the leakage current profile. We first focus on the discussion of SiGe Body [28, 29]. We varied the SiGe Body thickness of the Nanosheet iTFET from 5 to 15 nm. The results show that at a SiGe Body thickness of 5 nm, interface traps have a noticeable impact on the device. However, as the SiGe Body thickness increases, the influence of traps gradually diminishes, especially when SiGe Body = 15 nm, the device is almost entirely unaffected by traps, as shown in Fig. 23a–d. It’s essential to note that since our device is primarily line tunneling-dominated, increasing the SiGe Body thickness reduces the device’s line tunneling control capability. Besides increasing the device volume, the subthreshold swing also increases accordingly. As mentioned earlier, when SiGe Body > 10 nm, the SS exceeds 60 mV/dec. Considering these results, increasing the SiGe Body thickness is not an effective way to mitigate the impact of traps.

Fig. 23
figure 23

ID–VG characteristic curves with SiGe Body thicknesses of a 5nm, b 7nm, c 10nm, d 15nm, as a function of different interface trap densities of the Nanosheet iTFET

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While increasing the drain length to lengthen the distance between the gate and drain can effectively reduce IOFF, which is a well-known technique [30], it becomes evident that adjusting the drain length is not an effective means to mitigate the impact of traps, especially when considering the presence of interface traps. This is illustrated in Fig. 24. Clearly, the adjustment of drain length is not an effective approach to address the influence of traps.

Fig. 24
figure 24

ID–VG characteristic curves with different Drain length of the Nanosheet iTFET

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By altering the source metal, we indirectly adjusted the Schottky barrier height (φb) [17]. At (φb) = 0.9 eV, the device achieves better ION/IOFF and lower SS. However, when considering the non-ideal effects of interface traps, increasing (φb) not only effectively enhances ION/IOFF but also has a significant impact on traps in Fig. 25a–c. Therefore, adjusting (φb) resulted in substantial trap influence at (φb) = 0.9 eV, and almost complete immunity to traps at (φb) = 0.7 eV. However, at (φb) = 0.7 eV, the tunneling-dominant mechanism is not ideal. Consequently, we consider (φb) = 0.8 eV to be the most suitable choice for the device. This option minimizes the impact of traps while preserving favorable tunneling characteristics.

Fig. 25
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ID–VG characteristic curves with Schottky barrier heights of a 0.7 eV, b 0.8 eV, c 0.9 eV, as a function of diverse interface trap densities of the Nanosheet iTFET

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We applied (φb) = 0.8 eV to all three devices and conducted a device analysis under different interface trap conditions in Fig. 26. The results indicate that, without considering interface traps, the PIN TFET using the point tunneling mechanism exhibits superior ION/IOFF. However, with the increase in interface trap concentration, Nanosheet iTFET and Fin iTFET, utilizing the line tunneling mechanism, outperform in terms of ION/IOFF, as shown in Fig. 27a. Regarding subthreshold swing (SS), all three devices show an increase as the interface trap concentration rises. Even at a relatively high interface trap concentration of 1 \(\times 10\)12, PIN TFET maintains an SS below 60 mV/dec, while Nanosheet iTFET and Fin iTFET demonstrate commendable performance with an SS of 33 mV/dec in Fig. 27b.

Fig. 26
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ID–VG characteristic curves of the three devices with different interface trap densities at Schottky barrier height = 0.8 eV

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Fig. 27
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a ION/IOFF ratio of the three devices b SS with different interface trap densities at Schottky barrier height = 0.8 eV

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By comparing our device with stacked Nanosheet devices reported in recent years, our device demonstrates a lower subthreshold swing at lower power supply voltages in Table 3 and Fig. 28 [3, 31,32,33,34]. While the ION/IOFF ratio may be slightly lower compared to other reference literature, we believe that users can choose an appropriate number of stacking layers based on their specific ION requirements, thus addressing the challenge of maintaining a low subthreshold swing while improving the issue of too low ION/IOFF.

Table 3 Comparison of the proposed Stacked nanosheet semiconductor devices
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Fig. 28
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Performance comparison of Stacked Nanosheet semiconductor devices

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4 Conclusion

In this thesis, we employ a line tunneling mechanism and applying Nanosheet stacking method, combined with iTFET technology. This has successfully achieved superior Band-to-Band characteristics, lower subthreshold swing, and higher ION. In terms of the fabrication process, using the line tunneling mechanism in iTFET allows Nanosheet iTFET to have a larger gate and source overlap area, compared to traditional Nanosheet MOSFETs of the same volume, thereby enhancing device performance. Within Nanosheet iTFET, we have also investigated SiGe Body thickness and SiGe Body concentration. The results indicate optimal device performance when SiGe Body = 3 nm and SiGe Body concentration is 1 \(\times\) 1018.

However, under non-ideal conditions, interface traps pose a significant challenge for TFETs. We conducted an in-depth study on interface traps and found that (φb) = 0.8 eV is the most suitable choice for the device. This not only effectively reduces the impact of traps but also maintains excellent tunneling characteristics. Additionally, we compared PIN TFET utilizing point tunneling and Nanosheet iTFET and Fin iTFET utilizing line tunneling. Ultimately, we discovered that Nanosheet iTFET or Fin iTFET with line tunneling not only achieves higher ION/IOFF but also reaches a minimum SS of 17 mV/dec. Even considering interface traps, the worst-case scenario for SS remains below 33 mV/dec. This comprehensive comparison contributes valuable insights for the design and optimization of stacked semiconductor devices.

In future applications such as IoT and AI devices, the increasing demand for higher voltages has become an unavoidable issue in terms of device power consumption. Maintaining high performance and steep subthreshold swing becomes crucial as the supply voltage decreases. Based on the results above, we believe that Nanosheet iTFET will become the preferred component for low-power and fast-switching applications in the future.