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Microstructural and Electronic Properties of Rapid Thermally Grown MoS2|Silicon Hetero-Junctions with Various Process Parameters

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Abstract

Molybdenum disulphide (MoS2) has gained tremendous attention due to its tunable semiconducting properties and versatile applications in future electronic and optoelectronic devices. Here, MoS2 thin films were grown by adopting rapid thermal process. The process parameters like time and temperature have been systematically varied to modulate the morphological, microstructural, and electronic properties of MoS2 thin films. A uniform morphology has been observed from FESEM images. The microstructural study was further carried out using XRD pattern and Raman spectra. The intensity of (002) XRD characteristic peak at 2θ = 14.1° is found to be increased, whereas the FWHM values are reduced with the growth time and process temperature. The improvement of crystallinity of the MoS2 thin films with growth temperature is attributed to the decrease in the FWHM values of the characteristic Raman peaks, \(E_{{2g}}^{1}\) and A1g. The dependence of hetero-junction characteristics such as ideality factor η, built-in voltage Vbi, and carrier concentration on the growth parameters was evaluated using current-voltage and capacitance–voltage measurements. The films grown at 900°C for 5 min have possessed carrier concentration of 5.21 × 1016 cm–3, with 0.55 V as Vbi, and η is found to be 2.04 for MoS2|Si hetero-junction. The decrease in the carrier concentration, η, and Vbi in MoS2|Si hetero-junction with the increase in the growth temperature has been ascribed to the reduction in the defect states due to enhancement in the sulfurization.

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ACKNOWLEDGMENTS

This work was supported by Defence Research and Development Organisation (DRDO), India sponsored Extramural Research and Intellectual Property Rights (ERIP) project (ERIP/ERJ201701014/M/0l/1748).

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Pradhan, D., Kar, J.P. Microstructural and Electronic Properties of Rapid Thermally Grown MoS2|Silicon Hetero-Junctions with Various Process Parameters. Semiconductors 55, 948–959 (2021). https://doi.org/10.1134/S1063782621060117

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