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A Low-Temperature SiO2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor

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Abstract

In this paper, a low-temperature SiO2 interfacial layer preparation using rapid thermal oxidation (RTO) process for gate-all-around (GAA) nanosheet (NS) based input-output (I/O) transistor is explored in detail. After preparing high-quality thick SiO2 IL at 600℃, its MOS capacitor with W/TiN/HfO2/SiO2/Si substrate structure achieves well behaved multi-frequency capacitance-voltage characteristics, low leakage current, low interfacial trap density (Dit), and excellent time-dependent dielectric breakdown. For instance, its gate leakage under flatband voltage (Vfb) -1 V is only 2.48 × 10–9 A/cm2, its minimum Dit reaches 5.1 × 1010 eV−1 cm−2, and its ten-year lifetime effective voltage can reach 3.62 V at a failure rate of 0.01%. Moreover, a GAA NS based I/O device with a healthy gate stack is successfully prepared using this low-temperature SiO2 interfacial layer and its gate leakage is below 1 × 10–13 A, approaching the detection limit. These above results indicate that this low-temperature RTO-grown SiO2 IL has excellent quality and can meet the requirements of GAA NSs I/O transistors.

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Data Availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

We thank the Integrated Circuit Advanced Process Center of the Institute of Microelectronics of the Chinese Academy of Sciences for the samples fabricated on their 200 mm CMOS platform.

Funding

This work is supported by Strategic Priority Research Program of Chinese Academy of Sciences (Grant no. XDA0330304).

Author information

Authors and Affiliations

  1. School of Applied Science, Bei**g Information Science and Technology University, Bei**g, 100192, China

    Huaizhi Luo & Yan Li

  2. Integrated Circuit Advanced Process Center, Institute of Microelectronics of the Chinese Academy of Sciences, Bei**g, 100029, China

    Huaizhi Luo, Fei Zhao, ** Zhang, Wenjun **ong, **aotong Mao & Yongliang Li

  3. High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Bei**g, 100029, China

    Shengkai Wang

Authors
  1. Huaizhi Luo
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  2. Yan Li
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  3. Fei Zhao
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  4. ** Zhang
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  5. Shengkai Wang
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  6. Wenjun **ong
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  7. **aotong Mao
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  8. Yongliang Li
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Contributions

HuaiZhi Luo, ** Zhang, and YongLiang Li: Conceptualization, methodology, and formal analysis; Yan Li, WenJuan **ong, and ShengKai Wang: validation; HuaiZhi Luo, Fei Zhao, and **aoTong Mao: writing—original draft preparation; Yan Li: writing—review and editing; YongLiang Li: funding acquisition.

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Correspondence to Yan Li or Yongliang Li.

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Luo, H., Li, Y., Zhao, F. et al. A Low-Temperature SiO2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor. Silicon 16, 1619–1625 (2024). https://doi.org/10.1007/s12633-023-02789-6

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