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Design and FPGA implementation of mixed VVC/HEVC CABAC decoding

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Abstract

CABAC (Context-based Adaptive Binary Arithmetic Coding) is a single operation mode for entropy coding in the two last video coding standards VVC (Versatile Video Coding) and HEVC (high-efficiency video coding). Otherwise, the CABAC+ used in VVC have been improved and partially changed compared to that used in HEVC. For high-resolution applications, the pick of one bin/cycle is not sufficient and it is a very challenging task to implement pipeline, parallel and mixed CABAC decoding architecture by simply adding more stages due to the data dependencies which and cause it to be the throughput bottleneck for video decoding. Mainly, the CABAC decoder is based on three stages: CSM (Context Selection and Modeling), BAD (Binary Arithmetic Decoding) and DBZ (De-binarization). Where the CSM and BAD adopted in CABAC VVC are changed compared to that used in CABAC HEVC. Consequently, in order to improve the CABAC decoder throughput with good area cost, new mixed design of CABAC MxVH_CABAC on a FPGA is proposed that can be support the SEs (syntax elements) in two recent standards VVC and HEVC respectively. This work is designed, described in VHDL language and implemented on FPGA Virtex-7. As result, the throughput is improved in our mixed design MxVH_CABAC and ranging between 166.33 Mbins/s and 665.32 Mbins/s with gain in area cost equal to 17.24% compared to those consumed in the both proposed designs CABAC_HEVC and CABAC_VVC. Additionally, the efficiency of MxVH_CABAC is about 0.069 Mbins/s/LUTs and it is better than those obtained in the other works in literature.

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A statement on how any datasets used can be accessed. This declaration is “not applicable”.

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Funding

Details of any funding received. This declaration is “not applicable”.

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Authors and Affiliations

  1. Research Laboratory in Renewable Energies and Materials, University Yahia Fares of Medea, 26000, Medea, Algeria

    Wahiba Menasri & Abderrezak Gacemi

  2. Research Laboratory on Electricale Engenering and Automatic, University Yahia Fares of Medea, 26000, Medea, Algeria

    Abdelkader Morsli

  3. Faculty of Electronic and Informatic, Laboratory of Image Processing and Radiation, USTHB, BP 32 El Alia, Bab Ezzouar Algiers, Algeria

    Abdallah Skoudarli

Authors
  1. Wahiba Menasri
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  2. Abdelkader Morsli
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  3. Abdallah Skoudarli
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  4. Abderrezak Gacemi
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A. Wahiba Menasri. B. Abdelkader Morsli. C. Abdallah Skoudarli. D. Abderrezak GACEMI.

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Correspondence to Wahiba Menasri.

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Menasri, W., Morsli, A., Skoudarli, A. et al. Design and FPGA implementation of mixed VVC/HEVC CABAC decoding. SIViP (2024). https://doi.org/10.1007/s11760-024-03242-w

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  • DOI: https://doi.org/10.1007/s11760-024-03242-w

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