Investigation of asymmetric degradation in electrical properties of a-InGaZnO thin-film transistor arrays as a function of channel width-to-length aspect ratio

Abstract

We report the effect of variation of the channel width-to-length aspect ratio on the negative bias stress instability and the impact of the source/drain contact resistance on the electrical properties of amorphous-InGaZnO (IGZO) thin-film transistor (TFT) arrays. An asymmetric degradation of the threshold voltage (V_th) was observed over a wide range of negative stress bias in the IGZO TFT arrays. The lowest ∆V_th of 0.8 V and good stability with an increase in stress time were observed for the array having the channel aspect ratio of ~ 1.5, whereas the highest ∆V_th of 5.2 V was observed for the array having the channel aspect ratio of ~ 2.5. The drain-induced barrier lowering (DIBL) mechanism and the transmission line method (TLM) were used to investigate this abnormal degradation. The maximum DIBL of 50.2 mV/V was calculated for the array having a channel width/length of 4.4/11 μm. Application of the TLM revealed a channel resistance of 10.4 kΩ μm at a small gate bias of 0.5 V. Degradation of the electrical properties was observed for the array having an aspect ratio of 2.5 owing to poor ohmic contact with the channel. This investigation suggests that proper selection of the aspect ratio is important in the design of small-scale TFT arrays, as it can help to reduce the degradation of the electrical properties at a smaller dimension. Short-channel effects such as electron trap** and parasitic resistances can be minimized via improvement of the bias stress instability by use of a width-to-length aspect ratio of ~ 1.5. The findings in this report are beneficial for designing ultra-high-definition active-matrix displays.