Abstract
In modern society, rapidly change the technology of different applications such as Image processing (IP) and Digital Signal Processing (DSP) applications, etc., low power and high-speed Multiplier (MUL) play a major role in IP applications like biomedical and wireless communication. This paper mainly gives a systematic review of approximate multipliers (AMs) more used for sha** and smoothing applications. Also, explain systematic results of different AMs mention other research and focus on rounding based AM. Finally, this paper compares the results and gives the merits and demerits of different AMs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Schulte MJ, Swartzlander E (1999) Truncated multiplication (TM) with correction constant. IEEE Trans Electron Comput 41(3):388–396
Kidambi SS (1996) Area efficient multipliers for digital signal processing. IEEE Trans Circuits Syst 11: Analog Digit signal Process 43(2):90–95
Hong S, Kim S (1999) Low power parallel multiplier (novel multiplier) design for DSP application through coefficient optimization. In: Proceeding on 12th annual IEEE international ASIC/SOC conference, Washington, DC, USA, pp 286–290
Kelly DR, Phillips BJ (2009) Approximate signed binary integer multipliers for arithmetic data value speculation. IEEE Trans Integr Tech Circuits 992:255–265
Kyaw KY, Goh WL (2010) Low-power high-speed multiplier for error tolerant application. In: Proceeding on IEEE international conference of electronic devices and solid-state circuits (EDSSC), Hong Kong, China, pp 1–4
Mahdiani HR, Ahmadi A (2010) Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans Circuits Syst: Regul Pap 57(4):850–862
Kulkarni P, Gupta P (2011) Trading accuracy for power with an under-designed multiplier architecture. IEEE Trans Electron Circuits 56(68):1–7
Venkatesan R, Agarwal A, Roy K (2011) MACACO: modeling and analysis of circuits for approximate computing. In: Proceeding on IEEE/ACM international conference on computer-aided design (ICCAD), San Jose, CA, USA, pp 667–673
Kahng AB, Kang S (2012) Accuracy-configurable adder (ACA) for approximate arithmetic designs. In: Proceeding on DAC design automation conference, San Francisco, CA, USA, pp 820–825
Alioto M (2012) Ultra-low power VLSI circuit design demystified and explained. IEEE Trans Circuits Syst: Regul Pap 59(1):3–29
Liang J, Han J, Lombardi F (2013) New metrics for the reliability of approximate and probabilistic adders. IEEE Trans Comput 62(9):1760–1771
Lin C-h, Lin I-C (2013) High accuracy approximate multiplier with error correction. In: Proceeding on IEEE 31st international conference on computer design (ICCD), Asheville, NC, USA, pp 33–38
Gupta V (2013) Low power digital signal processing using approximate adders (RCA). IEEE Trans Comput-Aided Des Integr Circuits Syst 32(1):124–137
Bhardwaj K, Mane PS, Henkel J (2014) Power- and area-efficient approximate wallace tree multiplier (AWTM) for error-resilient system. In: Proceeding on 15th international symposium on quality electronic design, Santa Clara, CA, USA, pp 263–269
Momeni A, Han J, Montuschi P, Lombardi F (2015) Design and analysis of approximate compressors for multiplication. IEEE Trans Comput 64(4):984–994
Osta M, Ibrahim A, Valle M (2015) Approximate multipliers based on inexact adders for energy-efficient data processing. In: Proceeding on new generation of CAS (NGCAS), Genova, Italy, pp 125–128
Mukherjee S (2015) Energy efficient multipliers for high-speed DSP applications. Int J Comput Sci Mob Comput 4(6):66–75
Narayanamoorthy S, Moghaddam HA, Liu Z, Park T, Kim NS (2015) Energy-efficient approximate multiplication for digital signal processing and classification of applications. IEEE Trans Very Large Scale Integr 23(6):1180–1184
Akbari O, Kamal M, Afzali-Kusha A, Pedram M (2017) Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(4):1352–1361
Begum S, Vijaya Kumar M (2017) Design of FIR filter using rounding based approximate (ROBA) multiplier. Int J Sci Eng Technol Res 22(6):4483–4489
Venu Kumar K (2017)Implementation of ROBA multiplier using approximate multiplier for high-speed & energy-efficient DSP applications.Int J Innov Technol 5(9):1824–1828
Yasodha P (2018) Design of Roba multiplier using booth signed multiplier and Brent Kung adder. Int J Eng Sci Invent (IJESI) 7(4):8–14
Susi S (2018) Dynamic accuracy configurable 64 bit multipliers using dual-quality 4:2 compressors. J Emerg Technol Innov Res (JETIR) 7(5):1032–1041
Marimuthu D, Bharath S (2018) FPGA implementation of rounded based approximate multiplier for efficient performance of digital signal processing. In: Proceeding on international conference on progressive research in applied sciences, engineering and technology, India, pp 19–26
Tikkireddy S, Manikanta SVG (2018) Reliable and accurate low dense multipliers. Int J Eng Adv Res Sci Techno 3(2):689–696
Arya N, Rahul M (2018) A new trend in VLSI based multipliers for error resilient DSP applications. Int Res J Eng Technol (IRJET) 5(4):3866–3869
Nagajyothi NR, Ancia A (2018) A high-speed and energy-efficient Roba multiplier using LF adder. Pramana Res J 8(12):52–58
Venkateshwarlu M, Papa Rao Ch (2018) Low power design of cryptography by using ROBA multiplier. Int J Manag Technol Eng 8(11):2502–2508
Vaeztourshizi M, Kamal M, Afzali-Kusha A, Pedram M (2018) An energy-efficient, yet highly-accurate, approximate non-iterative divider. In: Proceedings of the international symposium on low power electronics and design (ISLPED ‘18). Association for Computing Machinery, New York, NY, USA, pp 1–6
Medha Gayathri I, Sindhoori P, Sravan Kumar Reddy P (2018) Design and synthesis of multiplier using dual quality 4:2 compressors with higher speed and lower power consumption. Int J Res Advent Technol 16(6):1082–1089
Jagadeeswara Rao E, Samundiswary P (2021) A review of approximate multipliers and its applications. In: Advances in automation, signal processing, instrumentation, and control. Lecture notes in electrical engineering. Springer, Singapore, pp 1381–1392
Nandan D, Kanungo J, Mahajan A (2017) An efficient VLSI architecture for Iterative Logarithmic Multiplier. In: Proceeding on IEEE 4th international conference on signal processing and integrated networks (SPIN), Noida, pp 419–423
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Rao, E.J., Krishna, K.M., Khasim, M., Anjaiah, T. (2022). Study of Architecture and Performance Analysis of Approximation Multipliers. In: Chakravarthy, V.V.S.S.S., Flores-Fuentes, W., Bhateja, V., Biswal, B. (eds) Advances in Micro-Electronics, Embedded Systems and IoT. Lecture Notes in Electrical Engineering, vol 838. Springer, Singapore. https://doi.org/10.1007/978-981-16-8550-7_2
Download citation
DOI: https://doi.org/10.1007/978-981-16-8550-7_2
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-8549-1
Online ISBN: 978-981-16-8550-7
eBook Packages: EngineeringEngineering (R0)