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Direct Cu to Cu Bonding and Alternative Bonding Techniques in 3D Packaging

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3D Microelectronic Packaging

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 64))

Abstract

This chapter provides insight into direct Cu to Cu bonding and summarizes several critical empirical results. After comparing solder-less Cu–Cu bonding with solder-based bonding, we introduce various Cu–Cu stacking/bonding schemes for different 3D integration applications. We then review a number of methods of low-temperature Cu–Cu bonding including: (a) thermo-compression bonding (diffusion bonding), (b) Cu–Cu bonding with passivation cap** layers, (c) surface-activated bonding (SAB) and (d) alternative bonding methods (e.g. Cu/dielectric hybrid bonding and Cu–Cu insertion bonding). The effects of surface activation, surface microstructures and characteristics, and surface passivation on Cu–Cu bonding are highlighted an– discussed to understand how bonding behavior depends on Cu surface cleanness, diffusion, temperature, compression pressure, and bonding atmosphere. Lastly, we briefly introduce the commercial equipment for Cu–Cu bonding for high-volume manufacturing and summarize with recommendations for future research directions.

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Notes

  1. 1.

    Process times targets depend on stacking process e.g. chip-on-chip (CoC), chip-on-wafer (CoW) or wafer-on-wafer (WoW) processes, equipment configuration and manufacturing embodiment and resulting throughput and Model of Record (MoR). For Cu–Cu process to be adopted in high-volume manufacturing (HVM), higher throughput and lower cost is required compared to established (and depreciated) solder-based processes.

  2. 2.

    Acquired by Tessera, now consolidated in Xperi and TiVo merger end of 2019.

  3. 3.

    Pre-tested and sorted chips, hence the nomenclature: “known good dies” (KGD’s)

  4. 4.

    http://www.leti-cea.com/cea-tech/leti/english/Pages/Welcome.aspx.

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Acknowledgements

The editors would like to thank Hualiang Shi and Debendra Mallik of Intel Corporation for their critical review of this Chapter.

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Authors and Affiliations

  1. The University of Tokyo, Tokyo, Japan

    Tadatomo Suga & Ran He

  2. Intel Corporation, Santa Clara, CA, USA

    George Vakanas

  3. IMEC, Louvain, Belgium

    Antonio La Manna

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  1. Tadatomo Suga
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  2. Ran He
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  3. George Vakanas
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Correspondence to George Vakanas .

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  1. Intel Corporation, Chandler, AZ, USA

    Yan Li

  2. Intel Corporation, Chandler, AZ, USA

    Deepak Goyal

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Suga, T., He, R., Vakanas, G., La Manna, A. (2021). Direct Cu to Cu Bonding and Alternative Bonding Techniques in 3D Packaging. In: Li, Y., Goyal, D. (eds) 3D Microelectronic Packaging. Springer Series in Advanced Microelectronics, vol 64. Springer, Singapore. https://doi.org/10.1007/978-981-15-7090-2_8

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