Abstract
Evolution in fabrication technology has allowed the transistors, gates, and connecting wires to be placed in more close proximity in a VLSI chip. The transistors and connecting wires are being placed at more close proximity, leading to the reduction of the interconnection delay as well as crosstalk noise between the overlap** wires. Minimization of crosstalk is an important constraint in computing routing solution of a channel instance. In this paper, first we present a survey of two heuristic algorithms for producing two-layer minimum crosstalk VH channel routing solution. Then, we concentrate on crosstalk minimization for producing three-layer HVH channel routing solution of a given channel instance. Two different algorithms to produce minimum crosstalk three-layer HVH channel routing solutions have been proposed in this paper. The results computed from each of the algorithms are very promising and far better than the results computed for several two-layer routing solutions. For very small number of nets, our algorithms can produce sometimes 100% crosstalk reduction.
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Acknowledgements
I would like to thank Institute of Engineering and Management, Salt Lake, Kolkata, West Bengal, for giving me a very good opportunity and encouragement to present this paper.
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Chakraborty, S. (2020). Crosstalk Minimization as a High-Performance Factor in Three-Layer Channel Routing. In: Mandal, J., Bhattacharya, D. (eds) Emerging Technology in Modelling and Graphics. Advances in Intelligent Systems and Computing, vol 937. Springer, Singapore. https://doi.org/10.1007/978-981-13-7403-6_56
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DOI: https://doi.org/10.1007/978-981-13-7403-6_56
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