Abstract
This paper presents a single-precision floating point (IEEE 754 standard) matrix multiplier module. This is constructed using subblocks, which include floating point adder and floating point multiplier. These subblocks are designed to achieve the goal of low power consumption. Different architectures of subblocks are compared on the basis of energy-delay product. Design and simulations have been performed for 180 and 45 nm technology node. Simulation results show that design of floating point matrix multiplier is better at 45 nm than 180 nm technology node in terms of lesser delay by 43% and energy-delay product by 97.86% at 1 V. Also, 45 nm technology cells occupy only 6.25% of the area as compared to 180 nm cells.
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Gargave, S., Agrawal, Y., Parekh, R. (2018). Single-Precision Floating Point Matrix Multiplier Using Low-Power Arithmetic Circuits. In: Garg, A., Bhoi, A., Sanjeevikumar, P., Kamani, K. (eds) Advances in Power Systems and Energy Management. Lecture Notes in Electrical Engineering, vol 436. Springer, Singapore. https://doi.org/10.1007/978-981-10-4394-9_67
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DOI: https://doi.org/10.1007/978-981-10-4394-9_67
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