Pipeline Decimal Multiplier Using Binary Multipliers

Abstract

Decimal multiplication became the common practice for human computations. The results of the digital computers which were used for the decimal arithmetic operations for various financial and commercial applications should be same when compared with the human made calculations. The slightest error in these calculations may arise greater complications and may cause severe damage. Thus, the importance of decimal computer arithmetic has recognized by the standard floating-point arithmetic IEEE-754 2008. Several design approaches have been proposed already for the decimal arithmetic circuits to perform various operations like decimal addition, multiplication, subtraction, and division. In recent times, significant amount of efforts has been put on the development of Decimal IP cores to reduce the bottleneck in reconfigurable computing architectures. In this article, the pipeline decimal multipliers using binary multiplier architecture has been proposed. The proposed pipelined decimal multiplier has increased the throughput significantly, by reducing overall propagation delay. The architecture is implemented in 8-and 16-bit decimal operands on SPARTAN-3E FPGA architecture. This also helps to understand that which FPGA Architecture is optimal for the proposed multiplier. The performance comparison between proposed pipeline and non-pipeline decimal multiplier using binary multiplier on various FPGA Architectures were also discussed.