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Hardware-Aware Compilation

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Handbook of Hardware/Software Codesign

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Abstract

Hardware-aware compilers are in high demand for embedded systems with stringent multidimensional design constraints on cost, power, performance, etc. By making use of the microarchitectural information about a processor, a hardware-aware compiler can generate more efficient code than a generic compiler while meeting the design constraints, by exploiting those highly customized microarchitectural features. In this chapter, we introduce two applications of hardware-aware compilers: a hardware-aware compiler can be used as a production compiler and as a tool to efficiently explore the design space of embedded processors. We demonstrate the first application with a compiler that generates efficient code for embedded processors that do not have any branch predictor to reduce branch penalties. To demonstrate the second application, we show how a hardware-aware compiler can be used to explore the Design Space of the bypass designs in the processor. In both the cases, the hardware-aware compiler can generate better code than a hardware-ignorant compiler.

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Authors and Affiliations

  1. Arizona State University, 85281, Tempe, AZ, USA

    Aviral Shrivastava & Jian Cai

Authors
  1. Aviral Shrivastava
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  2. Jian Cai
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Correspondence to Aviral Shrivastava .

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Editors and Affiliations

  1. Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Computer Science, Friedrich-Alexander-Universität Computer Science, Nürnberg, Germany

    Jürgen Teich

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Shrivastava, A., Cai, J. (2016). Hardware-Aware Compilation. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7358-4_26-1

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  • DOI: https://doi.org/10.1007/978-94-017-7358-4_26-1

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  • Print ISBN: 978-94-017-7358-4

  • Online ISBN: 978-94-017-7358-4

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