Abstract
A novel memory consistency model for thousand-core processors is presented. The model simplifies cache coherence for the full chip, and reduces cache design complexity. In addition, the model has the ability to describe the direct exchange of data on chip, thereby alleviating the off-chip memory bandwidth requirements. The paper gives a formal definition of the model, and proves that the model is sequentially consistent. All aspects of the definition are fully used in the process of proof, which means that there is no redundancy in the definition. Therefore, based on the split-range shared memory consistency model, a shared memory system can achieve high performance at low hardware cost. Meanwhile, the model is easy to be understood and used by programmers.
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Lyu, H., Zheng, F., **e, X. (2014). SRS: A Split-Range Shared Memory Consistency Model for Thousand-Core Processors. In: Wu, J., Chen, H., Wang, X. (eds) Advanced Computer Architecture. Communications in Computer and Information Science, vol 451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-44491-7_3
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DOI: https://doi.org/10.1007/978-3-662-44491-7_3
Publisher Name: Springer, Berlin, Heidelberg
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