Abstract
Over the last decades computer-aided engineering tools have been developed and improved in order to raise productivity in the chip design business. At the same time reconfigurable microelectronic devices known as field programmable gates arrays (FPGAs) evolved into powerful platforms for the implementation of complex embedded systems. Up to now, these design tools do not support a consistent design strategy for the development of side-channel resistant hardware implementations of cryptographic algorithms. In order to close this gap, we present a novel architecture denoted as Mutating Runtime Architecture and a dedicated design flow aimed to support system designers in implementing cryptographic devices hardened against side-channel attacks (SCA). Our contributions are generic in the sense that they allow to uniformly harden symmetric as well as asymmetric cryptographic algorithms against power analysis attacks. In addition to an introduction of fundamental concepts, construction methods for multiple countermeasures, and the resulting flexible cipher architecture, we present a case study.
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Notes
- 1.
SBox, MixColumn, AddRoundkey.
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Acknowledgements
This work was funded in part by DFG, the German science foundation, under grant no. HU620/12 within the DFG Priority Programme 1148 “Reconfigurable Computing Systems” in cooperation with CASED.
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Huss, S.A., Stöttinger, M. (2017). A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks. In: Mishra, P., Bhunia, S., Tehranipoor, M. (eds) Hardware IP Security and Trust. Springer, Cham. https://doi.org/10.1007/978-3-319-49025-0_8
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