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Fundamentals of Electromigration in Interconnects of 3D Packaging

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3D Microelectronic Packaging

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 57))

Abstract

Micro bumps, through Si vias (TSV), and redistribution layers (RDL) or back-end-of-line (BEOL) layers that connected to the TSV are unique interconnects connecting the stacked Si dies in 3D packaging. Electromigration (EM) failure has been a concern for these interconnects due to high current density and joule heating. In this chapter, the key EM failure modes in these interconnects are summarized. By leveraging the EM learning from flip chip first-level interconnect solder joints and damascene Cu interconnects, failure mechanisms and factors that modulate the EM of micro bumps, TSV, and its connected Cu layers are also summarized. The impact of the unique micro bump dimensions and structures on EM will be highlighted.

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Acknowledgment

The editors would like to thank Kwang-Lung Lin from National Cheng Kung University in Taiwan for his critical review of this chapter.

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  1. Intel Corporation, 5000 W. Chandler Blvd., Chandler, AZ, 85226, USA

    Pilin Liu

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  1. Pilin Liu
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Correspondence to Pilin Liu .

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Editors and Affiliations

  1. Intel Corporation, Chandler, Arizona, USA

    Yan Li

  2. Intel Corporation, Chandler, Arizona, USA

    Deepak Goyal

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Liu, P. (2017). Fundamentals of Electromigration in Interconnects of 3D Packaging. In: Li, Y., Goyal, D. (eds) 3D Microelectronic Packaging. Springer Series in Advanced Microelectronics, vol 57. Springer, Cham. https://doi.org/10.1007/978-3-319-44586-1_9

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  • DOI: https://doi.org/10.1007/978-3-319-44586-1_9

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