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High Performance Ternary Full Adder in CNFET-Memristor Logic Technology

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VLSI Design and Test (VDAT 2022)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1687))

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Abstract

This paper presents ternary unary operators and multiplexer circuits in carbon nanotube field effect transistor and memristor technology. The designed circuits can be used in designing ternary arithmetic circuits, a ternary full adder is proposed in this paper using ternary unary operators and multiplexers. The proposed circuits are simulated in Cadence Virtuoso using MOSFET-like CNFET and VTEAM memristor model. The proposed ternary full adder is having a savings of 17\(\%\) in the power delay product to the best existing designs. Noise margin analysis was carried out on the proposed circuits and proposed ternary full adder is having a good noise margin.

This work has been supported by the DST, Start up Research Grant - SRG/2021/001255.

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References

  1. Smith, K.C.: The prospects for multivalued logic: a technology and applications view. IEEE Trans. Comput. C–30(9), 619–634 (1981)

    Article  MathSciNet  MATH  Google Scholar 

  2. Raychowdhury, A., Roy, K.: Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005)

    Article  Google Scholar 

  3. Lin, S., Kim, Y.-B., Lombardi, F.: Design of a ternary memory cell using CNTFETs. IEEE Trans. Nanotechnol. 11(5), 1019–1025 (2012)

    Article  Google Scholar 

  4. Lin, S., Kim, Y.-B., Lombardi, F.: CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)

    Article  Google Scholar 

  5. Srinivasu, B., Sridharan, K.: Low-complexity multiternary digit multiplier design in CNTFET technology. IEEE Trans. Circuits Syst. II Express Briefs 63(8), 753–757 (2016)

    Google Scholar 

  6. Hurst, S.L.: Multiple-valued logic? Its status and its future. IEEE Trans. Comput. 33(12), 1160–1179 (1984)

    Article  Google Scholar 

  7. Karmakar, S., Jain, F.C.: Ternary static random access memory using quantum dot gate field-effect transistor. Micro Nano Lett. 10(11), 621–624 (2015)

    Article  Google Scholar 

  8. Kvatinsky, S., Ramadan, M., Friedman, E.G., Kolodny, A.: VTEAM: a general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs 62(8), 786–790 (2015)

    Google Scholar 

  9. Zangeneh, M., Joshi, A.: Design and optimization of nonvolatile multibit 1T1R resistive RAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(8), 1815–1828 (2013)

    Google Scholar 

  10. Kvatinsky, S., Belousov, D., et al.: MAGIC-memristor-aided logic. IEEE Trans. Circuits Syst. II Express Briefs 61(11), 895–899 (2014)

    Google Scholar 

  11. Kvatinsky, S., Satat, G., et al.: Memristor-based material implication (IMPLY) logic: design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2054–2066 (2013)

    Article  Google Scholar 

  12. Wang, X.-Y., et al.: High-density memristor-CMOS ternary logic family. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1), 264–274 (2020)

    Article  Google Scholar 

  13. Mohammed, M.U., Vijjapuram, R., Chowdhury, M.H.: Novel CNTFET and memristor based unbalanced ternary logic gate. In: 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1106–1109 (2018)

    Google Scholar 

  14. Miller, D.M., Thornton, M.A.: Multiple valued logic: concepts and representations. Synth. Lect. Digit. Circuits Syst. 2(1), 1–127 (2007)

    Article  Google Scholar 

  15. Srinivasu, B., Sridharan, K.: A synthesis methodology for ternary logic circuits in emerging device technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 64(8), 2146–2159 (2017)

    Article  Google Scholar 

  16. Vudadha, C., Surya, A., Agrawal, S., Srinivas, M.: Synthesis of ternary logic circuits using 2: 1 multiplexers. IEEE Trans. Circuits Syst. I Regul. Pap. 65(12), 4313–4325 (2018)

    Article  Google Scholar 

  17. Zahoor, F., Zulkifli, T.Z.A., Khanday, F.A., Zainol Murad, S.A.: Carbon nanotube and resistive random access memory based unbalanced ternary logic gates and basic arithmetic circuits. IEEE Access 8, 104 701–104 717 (2020)

    Google Scholar 

  18. Stanford University CNTFET model. Stanford University, Stanford, CA (2008). http://nano.stanford.edu/model_stan_cnt.htm

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Authors and Affiliations

  1. Indian Institute of Technology Mandi, Mandi, India

    Panasa Srikanth & B. Srinivasu

Authors
  1. Panasa Srikanth
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  2. B. Srinivasu
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Corresponding author

Correspondence to B. Srinivasu .

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Editors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Jammu, Jammu, India

    Ambika Prasad Shah

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology Surat, Surat, India

    Anand Darji

  4. Department of Computer Science and Engineering, Indian Institute of Technology Tirupati, Tirupati, India

    Jaynarayan Tudu

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Srikanth, P., Srinivasu, B. (2022). High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_35

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  • DOI: https://doi.org/10.1007/978-3-031-21514-8_35

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-21513-1

  • Online ISBN: 978-3-031-21514-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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