Abstract
This chapter deals with digital static timing analysis and implementation methodology, covering design corners definition, implementation corners selection, power grid with specific aspect added or changed with body-bias.
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Notes
- 1.
Further abbreviated (P, V, T, a, BB) space of static timing analysis.
- 2.
Example of failure: the BBGEN charge pump may fail to deliver the amount of negative voltage needed at cold for a given die.
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- 4.
One of us walked in this issue: we designed a CPU which was controlling its own bias on top of regular duty. The CPU needed about 3k cycles to boot and calculate it’s bias. In some cold startup case the CPU was dying before it could determine the bias it needed.
- 5.
This is a convergence problem, see Appendix B, Sect. B.1.8.
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Marchal, S., Riquet, D., Clerc, S. (2020). Digital Design Implementation Flow and Verification Methodology. In: Clerc, S., Di Gilio, T., Cathelin, A. (eds) The Fourth Terminal. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-39496-7_16
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DOI: https://doi.org/10.1007/978-3-030-39496-7_16
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