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GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security
Intellectual property (IP) security has emerged as a critical concern in semiconductor industries. In the domain of hardware IP security, logic...
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Integrated Circuit Testing Technology
Integrated circuit testing is continuously improved by the evolution of design, manufacturing, packaging, and new applications. Testing not only...
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Design of a Ternary Logic Processor Using CNTFET Technology
The design of a Ternary Logic Processor using CNTFETs (Carbon-Nanotube-Field-Effect-Transistor) is a challenging task, but it also has the potential...
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A novel clock recovering circuit to thwart clock glitch attacks on ring-oscillator-based TRNGs in edge devices like sensors
A novel clock recovering circuit is proposed and successfully validated by this study for a TRNG to thwart effectively all types of clock glitch...
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Combinational logic circuits based on a power- and area-efficient memristor with low variability
The saturation of complementary metal–oxide–semiconductor (CMOS) technology in terms of area and power efficiency has given rise to advanced research...
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FPGA Accelerated Parallel HsClone GA for Digital Circuit Configuration in CGP Format
The embryonic fabric architecture has emerged recently for realizing the digital circuits having scope of self-repair with minimal resources. Digital...
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Basics of Integrated Circuit Design
This section focuses on the IC design flow and the related process design kit (PDK). The design flow mainly consists of design specifications,...
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On the Layout-Oriented Investigation of Power Attack Hardness of Spintronic-Based Logic Circuits
High leakage power consumption has become one of the main concerns of data security protection with CMOS device scaling. Spintronic technology is one...
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Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic
In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS,...
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Design and implementation of high-performance 20-T hybrid full adder circuit
A new high-performance exclusive OR/exclusive NOR (XOR/XNOR) architecture with ten transistors is proposed in this work. Our research focused on...
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Multilayer Approach to Logic Locking
The rising need to safeguard semiconductor intellectual property (IP) from untrusted entities during the design and fabrication process has spurred...
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Real Time Detection of Partial Shading in the Photovoltaic Systems Using New Fuzzy Logic Technique
AbstractPhotovoltaic (PV) modules may not experience uniform solar irradiation due to partial shading caused by the shadows of trees, passing clouds,...
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π Junctions in Adiabatic Superconductor Logic Cells
AbstractRecently, adiabatic superconducting logic has been actively used to process broadband group signals in situations in which ultralow energy...
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Efficient Quantum Circuit for Karatsuba Multiplier
The fundamental element of quantum computing is the quantum circuit. An efficient quantum circuit saves quantum hardware resources by reducing the...
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Impact of Genetic Algorithm on Low Power QCA Logic Circuit with Regular Clocking
Pramanik, Amit Kumar Pal, Jayanta Sen, BibhashQuantum-dot Cellular Automata (QCA) is the alternative approach to synthesize the logic circuit with...
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FPGA Implementation of Ternary Multiplier Using Reconfigurable Logic
The multiplier circuit of the ALU is one of the most crucial parts of the computer. Therefore, a powerful computer might be built by optimising the...
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Exploring Circuit Design Topologies for RFETs
Designing logic gates based on emerging technologies is necessary as they form the building block for digital design. It lays the foundation to...
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Reliable and ultra-low power approach for designing of logic circuits
The principal design concern in today’s very large-scale integration (VLSI) industry is power dissipation. Power dissipation in a chip rises...
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An improved 1.8 V 4.05 ppm/°C curvature corrected bandgap reference circuit
In this paper a curvature corrected bandgap reference circuit is presented which uses folded cascode operation amplifier using beta multiplier as a...
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Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion
This study applies artificial neural networks (ANNs) to increase stuck-at and delay fault coverage of logic built-in self-test (LBIST) through test...
