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Hardware Implementation of a High-Speed Adaptive Filter Using a Combination of Systolic and Convex Architectures
In this paper, an improved high-speed adaptive filter is proposed and implemented using a field-programmable gate array platform. Specifically, a new...
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Massively Parallel Neural Processing Array (MPNA): A CNN Accelerator for Embedded Systems
Many hardware accelerators for Convolutional Neural Networks (CNNs) focus on accelerating only the convolutional layers but do not prioritize...
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Coarse-Grained Reconfigurable Array (CGRA)
Coarse-grained reconfigurable array (CGRA) is a promising class of spatial accelerator that offers high performance, energy efficiency, as well as...
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A Novel Method for Design and Implementation of Systolic Associative Cascaded Variable Leaky Least Mean Square Adaptive Filter for Denoising of ECG Signals
Electrocardiogram is the most essential diagnostic test for heart disease detection in this era, where it has low frequency and small amplitude,...
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Systolic optimized adaptive filter architecture designs for ECG noise cancellation by Vertex-5
The adaptive sign least mean square (SLMS) filter may change dynamically depending on the filter output. Noise cancellation is one of the most common...
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Flexible Systolic Hardware Architecture for Computing a Custom Lightweight CNN in CT Images Processing for Automated COVID-19 Diagnosis
Millions of deaths worldwide have been resulted throughout the COVID-19 pandemic, thus the need of diagnosing techniques for early disease stage has...
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Field-Programmable Gate Array Architecture
Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have grown more complex, more capable, and more diverse in...
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Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
The accelerators are gaining predominant attention in the HW/SW designs and embedded designs due to the less power consumption and parallel data...
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Implementation of Discrete Sine Transform Realization Though Systolic Architecture
In this paper, an efficient design approach is used for implementation of discrete sine transform (DST). A new algorithm for DST for N = 4n has been...
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Antenna Array and Feed-Backward Equalizer as Single Adaptive Device
AbstractThis paper considers an adaptive antenna array (AAA) with its weight factors combined with those of Feed-Forward (FF) part of a channel...
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FPGA Design of a Variable Step-Size Variable Tap Length Denlms Filter with Hybrid Systolic-Folding Structure and Compressor-Based Booth Multiplier for Noise Reduction in Ecg Signal
Electrocardiogram (ECG) is a critical type of biological signal that brings significant data about the patients. The morphological structure of ECG...
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Systolic anterior motion in hypertrophic cardiomyopathy: a fluid–structure interaction computational model
We present direct numerical simulations for the pathophysiology of hypertrophic cardiomyopathy of the left ventricle of the human heart. This...
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Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic
In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on...
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Optimisation of FPGA-Based Designs for Convolutional Neural Networks
Convolutional neural networks (CNN) is a widely known deep learning architecture and achieves higher accuracies in speech processing and computer...
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Systolic FIR Filter with Reduced Complexity SQRT CSLA Adder
For real-time signal processing using special-purpose array processors and pipeline processing to maximize the processing concurrency are the only...
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AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
Compute-bound problems like matrix-matrix multiplication can be accelerated using special purpose hardware scheme such as Systolic Arrays (SAs)....
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Floating Point Implementation of the Improved QRD and OMP for Compressive Sensing Signal Reconstruction
In this paper, the Floating-Point Core Architecture based QR decomposition is proposed for solving least square problems in the Orthogonal Matching...
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Performance-Driven LSTM Accelerator Hardware Using Split-Matrix-Based MVM
This paper proposes a new hardware approach for accelerating matrix vector multiplication (MVM) employing systolic array architecture and parallel...
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Systolic Arrays
This chapter reviews the basic ideas of systolic array, its design methodologies, and historical development of various hardware implementations. Two...
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High-speed emerging memories for AI hardware accelerators
Applications of artificial intelligence (AI) necessitate AI hardware accelerators able to efficiently process data-intensive and...
