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Grammatical Evolution of Complex Digital Circuits in SystemVerilog
The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount...
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Evolution of Complex Combinational Logic Circuits Using Grammatical Evolution with SystemVerilog
Scalability problems have hindered the progress of Evolvable Hardware in tackling complex circuits. The two key issues are the amount of testing (for...
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Hybrid learning scenario path selection and abstraction framework for smart verification of complex SoCs
The universal verification methodology (UVM) testbench utilizes the bus interface to access the design under verification (DUV) and registers using...
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CHA: Supporting SVA-Like Assertions in Formal Verification of Chisel Programs (Tool Paper)
We present CHA, an assertion language and verification tool for Chisel programs built on top of ChiselTest, where we extend the Chisel assertion...
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A Case Study in the Automated Translation of BSV Hardware to PVS Formal Logic with Subsequent Verification
We previously developed a method of formal hardware verification that automatically translates hardware descriptions encoded in Bluespec...
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Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations
There is a definite upward trend in the number of cellular communication nodes that, together with high rate of digital content transactions, led to...
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A DSL and MLIR Dialect for Streaming and Vectorisation
This work addresses the contemporary challenges in computing, caused by the stagnation of Moore’s Law and Dennard scaling. The shift towards...
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From the Standards to Silicon: Formally Proved Memory Controllers
Recent research in both academia and industry has successfully used deductive verification to design hardware and prove its correctness. While tools...
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Chebyshev approximation technique: analysis and applications
In many situations, exact solutions to complex problems may be challenging or impossible to obtain, making approximation techniques necessary for...
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Scalable and Efficient Architecture for Random Forest on FPGA-Based Edge Computing
This paper proposes a scalable and efficient architecture to accelerate random forest computation on FPGA devices targeting edge computing platforms....
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\(\mathrm {DD\text {-}MPU}\) : Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips
The integration of potentially untrustworthy intellectual property (IP) blocks into a System-on-Chip (SoC) poses significant risks, including data...
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A Versatile and Unified HQC Hardware Accelerator
This work presents a hardware design for the post-quantum Hamming Quasi-Cyclic (HQC) Key Encapsulation Mechanism (KEM). We present a novel unified...
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Simulation-based evaluation of bit-interaction side-channel leakage on RISC-V: extended version
Masking is a promising countermeasure against side-channel attacks, and share slicing is a masking technique that stores all shares in a single...
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A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography
This research topic aims to investigate system models and hardware architectures of Computed Tomography scanners to provide the plug-and-play...
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Building a System
Transistors and other key components have driven the digital revolution of the last four decades, fueling innovation across all scientific...
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Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters
The reliability of High-Performance Computing (HPC) systems is an essential concern due to their massive size and the complexity of their operation....
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A Functional Verification Methodology for Highly Parametrizable, Continuously Operating Safety-Critical FPGA Designs: Applied to the CERN RadiatiOn Monitoring Electronics (CROME)
Electronic systems that are related to human safety need to comply to strict international standards such as the IEC 61508. We present a functional...
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Reduction-Free Multiplication for Finite Fields and Polynomial Rings
The complexity of the multiplication operation over polynomial rings and finite fields drastically changes with the selection of the defining...
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Design and Implementation of Built-In Self-Test (BIST) Master Slave Communication Using I2C Protocol
The IIC protocol (inter-integrated circuit) is a communication bus protocol that allows many masters and slaves to communicate with each other. The...
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Hardware Isolation Support for Low-Cost SoC-FPGAs
In the last years, System-on-Chip (SoC)-FPGAs have been widely used in Mixed-Criticality Systems, where multiple applications with different...