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Deductive Verification of Parameterized Embedded Systems Modeled in SystemC
Major strengths of deductive verification include modular verification and support for functional properties and unbounded parameters. However, in...
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An Untimed SystemC Model of GoogLeNet
Deep learning and convolutional neural network (CNN) have been shown to solve image classification problems fast and with high accuracy. However,...
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Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0
With the growing complexity of embedded applications, system architects integrate more processors into System-on-Chip (SoC) designs. Since...
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Split’n’Cover: ISO 26262 Hardware Safety Analysis with SystemC
The development of safe hardware is a major concern in automotive applications. The parts 5 and 11 of the ISO 26262 define procedures and methods for...
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Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation
To preserve the SystemC semantics under parallel discrete event simulation, a compiler based approach statically analyzes race conditions in the...
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Advanced virtual prototy** for cyber-physical systems using RISC-V: implementation, verification and challenges
Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modeling (TLM) and are...
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Simulation of Timing Attacks and Challenges for Early Side-Channel Security Analysis
Side-channel attacks (SCA) enable attackers to gain access to non-disclosed information by measuring emissions of a system, e.g., timing,...
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Handling causality and schedulability when designing and prototy** cyber-physical systems
Cyber physical systems are built upon digital and analog circuits, making it necessary to handle different models of computation during their design...
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Minimizing Memory Contention in an APNG Encoder Using a Grid of Processing Cells
Modern processors experience memory contention when the speed of their computational units exceeds the rate at which data can be accessed in memory....
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Towards functional verifying a family of systemC TLMs
It is often the case that in the development of a system-on-a-chip (SoC) design, a family of SystemC transaction level models (TLM) is created. TLMs...
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A Modular SystemC RTOS Model for Uncertainty Analysis
Nowadays the complexity of embedded systems is constantly increasing and several different types of applications concurrently execute on the same...
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Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling
Very early in the hardware development lifecycle, highly abstract simulations are essential to evaluate the performance and functionality of complex...
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DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
The simulation of DRAMs (Dynamic Random Access Memories) on system level requires highly accurate models due to their complex timing and power...
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A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms
Predicting the performance of Artificial Neural Networks (ANNs) on embedded multi-core platforms is tedious. Concurrent accesses to shared resources...
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Combining Forces: How to Formally Verify Informally Defined Embedded Systems
Embedded systems are ubiquitous in our daily lives, and they are often used in safety-critical applications, such as cars, airplanes, or medical...
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High-level power estimation techniques in embedded systems hardware: an overview
Power optimization has become a major concern for most digital hardware designers, particularly in early design phases and especially in limited...
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DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses
The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power...
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Simulation and Modelling for Network-on-Chip Based MPSoC
As systems that can adapt their architecture and behavior in response to their environment become increasingly valuable in modern applications,...
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HTPA: a hybrid traffic pattern aware arbitration strategy for network on chip systems
The Network-on-Chip (NoC) is a communication infrastructure designed to integrate various components of a System-on-Chip (SoC) and connect multi-core...
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AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators
In recent years the growing popularity of Convolutional Neural Network(CNNs) has driven the development of specialized hardware, so called Deep...
