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Efficient tasks scheduling in multicore systems integrated with hardware accelerators
Multicore systems integrated with hardware accelerators provide better performance for executing real-time applications in time-critical fields, such...
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Int-Monitor: a model triggered hardware trojan in deep learning accelerators
Deep learning accelerators have domain-specific architectures, this special memory hierarchy and working mode could bring about new crucial security...
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Exploiting Hardware Accelerators in Clouds
In this chapter, we plan to provide an overview of cloud accelerators available on different cloud providers. We plan to introduce, show how to...
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Performance Accelerators
The Graphics Processing Unit (GPU) has become one of the most important types of hardware accelerators. It is designed to render 3D graphics and...
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Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques
With the recent advancements in high-performance computing, convolutional neural networks (CNNs) have achieved remarkable success in various vision...
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Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators
As a primary computation unit, a processing element (PE) is key to the energy efficiency of a convolutional neural network (CNN) accelerator. Taking...
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Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective
Graph processing has been widely used in many scenarios, from scientific computing to artificial intelligence. Graph processing exhibits irregular...
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A systematic study on benchmarking AI inference accelerators
AI inference accelerators have drawn extensive attention. But none of the previous work performs a holistic and systematic benchmarking on AI...
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Hardware Acceleration for SLAM in Mobile Systems
The emerging mobile robot industry has spurred a flurry of interest in solving the simultaneous localization and map** (SLAM) problem. However,...
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Programming bare-metal accelerators with heterogeneous threading models: a case study of Matrix-3000
As the hardware industry moves toward using specialized heterogeneous many-core processors to avoid the effects of the power wall, software...
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Heterogeneous Hardware
This chapter provides the necessary background on computer architecture in order to understand how hardware accelerators are programmed and execute...
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Hardware Acceleration
With Moore’s law and Dennard’s scaling no longer fueling the improvement in computing performance, new avenues for increasing performance are needed....
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Partitioning Dense Graphs with Hardware Accelerators
Graph partitioning is a fundamental combinatorial optimization problem that attracts a lot of attention from theoreticians and practitioners due to...
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FlexPDA: A Flexible Programming Framework for Deep Learning Accelerators
There are a wide variety of intelligence accelerators with promising performance and energy efficiency, deployed in a broad range of applications...
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Hardware acceleration of YOLOv7-tiny using high-level synthesis tools
FPGAs have emerged as a promising platform for implementing neural networks due to their reconfigurability, parallelism, and low power consumption....
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Performance analysis of multiple input single layer neural network hardware chip
An artificial neural network (ANN) is a computational system that is designed to replicate and process the behavior of the human brain using neuron...
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Application of the Piecewise Linear Approximation Method in a Hardware Accelerators of a Neural Networks Based on a Reconfigurable Computing Environments
This paper considers the application of piecewise linear approximation in hardware accelerators of neural networks built according to the concept of...
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Programming Heterogeneous Hardware via Managed Runtime Systems
The last chapter described the challenges posed by programming hardware accelerators from managed programming languages, such as Java, C#, Python, or...
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Hardware Description Language Enhancements for High Level Synthesis of Hardware Accelerators
High level synthesis of hardware accelerators is one of the many complex hardware operations that unfortunately cannot be efficiently performed with...
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A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators
This paper introduces a configurable Activation Function (AF) that utilizes ROM/ Cordic architecture to generate sigmoid and tanh with varying bit...