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Boosting Both Robustness and Hardware Efficiency via Random Pruning Mask Selection
Deep neural networks (DNNs) are notorious for two key drawbacks: the vulnerability against adversarial attacks and the prohibitive cost of storage...
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A Hardware Trojan Exploiting Coherence Protocol on NoCs
Intellectual property (IP) has been used in Network on chips (NoCs) for reducing costs and shortening the time to market. However, there is a...
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Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography
Hybrid key encapsulation is in the process of becoming the de-facto standard for integration of post-quantum cryptography (PQC). Supporting two...
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Performance Modelling-Driven Optimization of RISC-V Hardware for Efficient SpMV
The growing need for inference on edge devices brings with it a necessity for efficient hardware, optimized for particular computational kernels,...
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A systematic literature review on hardware implementation of artificial intelligence algorithms
Artificial intelligence (AI) and machine learning (ML) tools play a significant role in the recent evolution of smart systems. AI solutions are...
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Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC
FPGA-SoCs are heterogeneous embedded computing platforms consisting of reconfigurable hardware and high-performance processing units. This...
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Reconfigurable spatial-parallel stochastic computing for accelerating sparse convolutional neural networks
Edge devices play an increasingly important role in the convolutional neural network (CNN) inference. However, the large computation and storage...
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Nacc-Guard: a lightweight DNN accelerator architecture for secure deep learning
Recent breakthroughs in artificial intelligence and deep neural networks (DNNs) have produced an explosive demand for computing platforms equipped...
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High-Level Synthesis of Memory Systems for Decoupled Data Orchestration
With the end of Dennard scaling and the slowdown in Moore’s law, domain-specific hardware accelerators are increasingly popular. Although...
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ACTION: Automated Hardware-Software Codesign Framework for Low-precision Numerical Format SelecTION in TinyML
In this paper, a new low-precision hardware-software codesign framework is presented, to optimally select the numerical formats and bit-precision for...
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POAS: a framework for exploiting accelerator level parallelism in heterogeneous environments
In the era of heterogeneous computing, a new paradigm called accelerator level parallelism (ALP) has emerged. In ALP, accelerators are used...
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2L-3W: 2-Level 3-Way Hardware–Software Co-verification for the Map** of Convolutional Neural Network (CNN) onto FPGA Boards
FPGAs have become a popular choice for deploying Convolutional Neural Networks (CNNs). As a result, many researchers have explored the deployment and...
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Hardware Acceleration for 1D-CNN Based Real-Time Edge Computing
One-dimensional convolutional neural network (1D-CNN) has a major advantage of low-cost implementation on edge devices, for time series...
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On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs
OpenCL is used in contemporary FPGA High-level Synthesis (HLS) design tools for the development of the host-side code which controls the data...
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Hardware-Centric AutoML for Mixed-Precision Quantization
Model quantization is a widely used technique to compress and accelerate deep neural network (DNN) inference. Emergent DNN hardware accelerators...
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Performance-oriented FPGA-based convolution neural network designs
Convolutional neural network (CNN) is the most well-known algorithm that it has been widely utilized in the applications of the image recognition and...
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ReCSA: a dedicated sort accelerator using ReRAM-based content addressable memory
With the increasing amount of data, there is an urgent need for efficient sorting algorithms to process large data sets. Hardware sorting algorithms...
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An Efficient Cryptographic Accelerators for IoT System Based on Elliptic Curve Digital Signature
Given the importance of security requirements in today’s Internet of Things (IoT) landscape, this study focuses on enhancing the security of IoT...
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On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS \(^{64}\)
Many papers proposed the execution of real-time tasks on FPGA hardware. Most of these works do not demonstrate fully working systems and suffer from...
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Factorized solution of generalized stable Sylvester equations using many-core GPU accelerators
We investigate the factorized solution of generalized stable Sylvester equations such as those arising in model reduction, image restoration, and...
