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26 Result(s)
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Sharad Malik
Circuits and Systems
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Chapter
Post-Silicon Fault Localization with Satisfiability Solvers
This chapter covers techniques to localize faults in integrated circuits by means of automated satisfiability solvers. These techniques aim at identifying fault candidates for an erroneous execution trace by s...
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Chapter
Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions
This chapter describes a methodology for system-level security verification of modern Systems-on-Chip (SoC) designs. These designs comprise interacting intellectual property (IP) blocks which are often sourced...
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Article
Specification and encoding of transaction interaction properties
Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES+ISSS ’03: proceedings of the 1st IEEE/...
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Article
Preface
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Chapter
Modeling and Integration of Peripheral Devices in Embedded Systems
This paper describes automation methods for device driver development in IP-based embedded systems in order to achieve high reliability, productivity, reusability and fast time to market. We formally specify d...
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Chapter
Power Analysis of Embedded Software: First Step Towards Software Power Minimization
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specifica...
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Article
Limits of Using Signatures for Permutation Independent Boolean Comparison
This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations. The permutation problem has several applications in the synthesis and verifi...
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Chapter
Sat and ATPG: Algorithms for Boolean Decision Problems
The problems of Boolean satisfiability (SAT) and automatic test pattern generation (ATPG) are strongly related — both in terms of application areas (pre-manufacturing design validation and post-manufacturing test...
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Chapter
Challenges in Code Generation for Embedded Processors
The emergence of integrated circuits in which both the program-ROM and the processor are integrated on a single die initiates a new era of problems for programming language compilers. In such a micro-architect...
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Article
A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library
We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this ...
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Book
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Chapter
Related Work in Timing Analysis for Embedded Software
The importance and the challenges in extreme case timing analysis of embedded software have been recognized by many researchers. Numerous analysis techniques have been proposed to solve the issues in program p...
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Chapter
Conclusions
The growth in software and hardware complexity demands more sophisticated system verification tools. For real-time systems, the critical property to be verified is that the system response time is within the s...
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Chapter
Introduction
Embedded systems are characterized by the presence of processors running application specific programs. They differ from traditional digital systems, in which most of the system functionality is implemented in...
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Chapter
Microarchitecture Modeling
The tightness of a program’s estimated bound depends on the accuracy in both path modeling and instruction timing modeling. In Chapter 3, we have shown that program path analysis models the set of feasible exe...
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Article
Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis
We address the problem of code generation for embedded DSP systems. In such systems, it is typical for one or more digital signal processors (DSPs), program memory, and custom circuitry to be integrated onto a...
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Chapter
Program Path Analysis
In Chapter 1, we described how the execution time of a program depends on the flow of the program and also the timing properties of the hardware. In this chapter, we will focus on analyzing the flow of the pro...
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Chapter
A Retargetable Timing Analysis Tool — Cinderella
We have implemented the timing analysis technique described in the previous two chapters in a tool called Cinderella. Cinderella automatically formulates the ILP problem and passes it to the ILP solver. With C...
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Article
Instruction level power analysis and optimization of software
The increasing popularity of power constrained mobile computers and embedded computing applications drives the need for analyzing and optimizing power in all the components of a system. Software constitutes a ...
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Chapter
Instruction Level Power Analysis and Optimization of Software
The increasing popularity of power constrained mobile computers and embedded computing applications drives the need for analyzing and optimizing power in all the components of a system. Software constitutes a ...
