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Chapter
Code Generation and Optimization Techniques for Embedded Digital Signal Processors
The advent of 0.5μ processing that allows for the integration of 5 million transistors on a single integrated circuit has brought forth new challenges and opportunities in embedded-system design. This high lev...
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Chapter
Performance Analysis of Embedded Systems
Embedded computer systems are characterized by the presence of one or more processors running application specific software. A large number of these systems must satisfy performance constraints in addition to ...
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Chapter and Conference Paper
Cinderella: A retargetable environment for performance analysis of real-time software
Real-time systems are characterized by the presence of timing constraints that a task must be completed within a given deadline. In this paper, we present a complete environment for determining best-case and w...
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Chapter and Conference Paper
Solving boolean satisfiability with dynamic hardware configurations
Boolean satisfiability (SAT) is a core computer science problem with many important commercial applications. An NP-complete problem, many different approaches for accelerating SAT either in hardware or softwar...
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Chapter and Conference Paper
Exploiting Retiming in a Guided Simulation Based Validation Methodology
There has been much interest recently in combining the strengths of formal verification techniques and simulation for functional validation of large designs [6].Typically, a formal test model is first obtained fr...
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Chapter and Conference Paper
Embedded Software Implementation Tools for Fully Programmable Application Specific Systems
A variety of diverse pressures are sha** how we will design digital systems in the near future. Shrinking geometries into the deep submicron range raise electrical design challenges that make it impossible t...
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Chapter and Conference Paper
Optimal Live Range Merge for Address Register Allocation in Embedded Programs
The increasing demand for wireless devices running mobile applications has renewed the interest on the research of high performance low power processors that can be programmed using very compact code. One way ...
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Article
Application of BDDs in Boolean matching techniques for formal logic combinational verification
Verifying that an implementation of a combinational circuit meets its golden specification is an important step in the design process. As inputs and outputs can be swapped by synthesis tools or by interaction ...
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Chapter and Conference Paper
The Quest for Efficient Boolean Satisfiability Solvers
The classical NP-complete problem of Boolean Satisfiability (SAT) has seen much interest in not just the theoretical computer science community, but also in areas where practical solutions to this problem enab...
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Chapter and Conference Paper
Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation
In this paper, we describe a new framework for evaluating Quantified Boolean Formulas (QBF). The new framework is based on the Davis-Putnam (DPLL) search algorithm. In existing DPLL based QBF algorithms, the p...
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Chapter and Conference Paper
Design Tools for Application Specific Embedded Processors
A variety of factors make it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). Consequently, programmable alternatives are more attrac...
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Chapter
Sat and ATPG: Algorithms for Boolean Decision Problems
The problems of Boolean satisfiability (SAT) and automatic test pattern generation (ATPG) are strongly related — both in terms of application areas (pre-manufacturing design validation and post-manufacturing test...
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Chapter
Challenges in Code Generation for Embedded Processors
The emergence of integrated circuits in which both the program-ROM and the processor are integrated on a single die initiates a new era of problems for programming language compilers. In such a micro-architect...
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Chapter and Conference Paper
The Quest for Efficient Boolean Satisfiability Solvers
The classical NP-complete problem of Boolean Satisfiability (SAT) has seen much interest in not just the theoretical computer science community, but also in areas where practical solutions to this problem enab...
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Chapter
Modeling and Integration of Peripheral Devices in Embedded Systems
This paper describes automation methods for device driver development in IP-based embedded systems in order to achieve high reliability, productivity, reusability and fast time to market. We formally specify d...
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Chapter
Power Analysis of Embedded Software: First Step Towards Software Power Minimization
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specifica...
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Chapter and Conference Paper
Symmetry Reduction in SAT-Based Model Checking
The major challenge facing model checking is the state explosion problem. One technique to alleviate this is to apply symmetry reduction; this exploits the fact that many sequential systems consist of intercha...
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Chapter and Conference Paper
Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems
The sequential circuit state space diameter problem is an important problem in sequential verification. Bounded model checking is complete if the state space diameter of the system is known. By unrolling the t...
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Chapter and Conference Paper
Zchaff2004: An Efficient SAT Solver
The Boolean Satisfiability Problem (SAT) is a well known NP-Complete problem. While its complexity remains a source of many interesting questions for theoretical computer scientists, the problem has found many...
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Article
Achieving Structural and Composable Modeling of Complex Systems
This paper describes a recently released, structural and composable modeling system called the Liberty Simulation Environment (LSE). LSE automatically constructs simulators from system descriptions that closel...