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  1. No Access

    Chapter and Conference Paper

    A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology

    This paper presents a 32 Gb/s low power little area re-timer with Phase Interpolator (PI) based Clock and Data Recovery (CDR). To further ensure signal integrity, both a Continuous Time Linear Equalizer (CTLE)...

    Zhengbin Pang, Fangxu Lv, Wei** Tang, Mingche Lai… in Advanced Computer Architecture (2020)

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    Article

    A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology

    This paper presents a 20 GHz subharmonic injection-locked clock multiplier (SILCM), which adopts a mixer based self-align injection timing control loop to guarantee the optimal injection point. In addition, to...

    Fangxu Lv, Xuqiang Zheng, Jianye Wang… in Analog Integrated Circuits and Signal Proc… (2019)

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    Chapter and Conference Paper

    Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network

    An approach based on Sparse Sub-band Basis (SSB) for compressive spectrum sensing in Wireless Sensor Network (WSN) is presented in this paper, considering the unsatisfactory accuracy and complex calculation of...

    Yu Wang, **cheng Zhang, Quan Wang, Fangxu Lv… in Advances in Wireless Sensor Networks (2015)