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3 Result(s)

within Chien-Chung Tsai Remove this filter Circuits and Systems Remove this filter

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  1. No Access

    Chapter

    On Concurrent Test of Core-Based SOC Design

    In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objectiv...

    Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai… in SOC (System-on-a-Chip) Testing for Plug an… (2002)

  2. No Access

    Article

    Synthesis of Scan Chains for Netlist Descriptions at RT-Level

    This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the orig...

    Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee… in Journal of Electronic Testing (2002)

  3. No Access

    Article

    On Concurrent Test of Core-Based SOC Design

    In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objectiv...

    Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai… in Journal of Electronic Testing (2002)