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within Conference Paper Remove this filter Sergio Feo-Arenis Remove this filter Mathematical Logic and Formal Languages Remove this filter Programming Languages, Compilers, Interpreters Remove this filter Software Engineering Remove this filter

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    Chapter and Conference Paper

    Reducing Quasi-Equal Clocks in Networks of Timed Automata

    We introduce the novel notion of quasi-equal clocks and use it to improve the verification time of networks of timed automata. Intuitively, two clocks are quasi-equal if, during each run of the system, they have ...

    Christian Herrera, Bernd Westphal… in Formal Modeling and Analysis of Timed Syst… (2012)

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    Chapter and Conference Paper

    Verification of GUI Applications: A Black-Box Approach

    In this paper, we propose to base the verification of a GUI application on a reference model used in black-box testing. The reference model is a formal model for the behavior of the GUI application. It is derived...

    Stephan Arlt, Evren Ermis, Sergio Feo-Arenis… in Leveraging Applications of Formal Methods,… (2014)

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    Chapter and Conference Paper

    On Global Scheduling Independency in Networks of Timed Automata

    Networks of timed automata are a widely used formalism to model timed systems. Models are often concise and convenient since timed automata abstract from many details of actual implementations. One such abstra...

    Sergio Feo-Arenis, Milan Vu**ović… in Formal Modeling and Analysis of Timed Syst… (2017)