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Physical Implementation
In this chapter, physical implementation step of FPGA application design will be investigated, including the well-known EDA steps: packing,...
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Semi-custom EDA
In modern computing systems, FPGAs are used as dedicated programmable accelerators (Che et al. [1], Zhang et al. [2], Cong et al. [3])....
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Introduction to Digital Twin Technologies in Transportation Infrastructure Management (TIM)
This chapter of “Digital Twin Technologies in Transportation Infrastructure Management” provides an introduction to the concept of Digital Twin in...
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Performance (Timing) Analysis
Timing analysis can be static or dynamic. Dynamic timing analysis (DTA) verifies functionality of the design by applying input vectors and checking...
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Introduction
Field programmable gate array (FPGA) is a typical semi-custom integrated circuit. The function of an FPGA is decided by both chip vendors and end...
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Neue Technologien und die Transformation der Textil- und Bekleidungsindustrie
Ausgehend von der aktuellen Transformation von der herkömmlichen Industriegesellschaft zur Wissensgesellschaft wird gezeigt, wie diese sich im...
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Marktsegment: digitale Bekleidung und virtuelle Räume
Untersuchungen mithilfe eines Onlineinterviews zum Kund*innenprofil für digitale Bekleidung haben ergeben, dass verschiedene...
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Digitale Bekleidung und virtuelle Welten – Hybridisierung des Bekleidungsmarktes
Es wird die digitale Bekleidung gepaart mit digitalen Models als eine Kollaboration von Gaming und Modedesign vorgestellt. Im Hinblick auf ihre...
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Digital Twin in TIM
This chapter of “Digital Twin Technologies in Transportation Infrastructure Management” focuses on the use of digital twin technology in TIM. The...
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Digital Twins Technologies
This chapter of “Digital Twin Technologies in Transportation Infrastructure Management” focuses on Digital Twin technologies and their various...
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Area Analysis
At FPGA chip design stage, area analysis/estimation is essential, just like ASIC chips. State-of-the-art FPGA area estimation techniques will be...
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Summary and Outlook
In this chapter, a brief look back of vanilla FPGA EDA is summarized. Commercial FPGA EDA tools for both chip design and application design is very...
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High-Level Synthesis
High-level synthesis (HLS) is the process of compiling a software program into a digital circuit. This chapter provides a view into the HLS design...
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Digital Twins in Design and Construction
Digital twins are gaining attention in the construction industry, as they offer several benefits such as reducing risks, improving quality, and...
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Digital Twins in Operation and Maintenance(O&P)
This chapter of “Digital Twin Technologies in Transportation Infrastructure Management” focuses on the role of Digital Twins in the operation and...
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Transportation Infrastructure Management
This chapter of “Digital Twin Technologies in Transportation Infrastructure Management” explores Transportation Infrastructure Management (TIM) in...
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Future Digital Twin in Infrastructure Management
In this chapter, “Future Digital Twin in Infrastructure Management,” discusses the advancements and potential future developments of digital twin...
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Design (Application Design) Modeling
Application design is the bridge between end user’s idea and FPGA’s functional units. Modeling it will build up application design data structure—the...
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Device (Chip Design) Modeling
This chapter provides the principles and implementations of FPGA device (chip design) modeling. FPGA device information can be derived from the...
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Bitstream Configuration
This chapter will introduce the final step of FPGA application design EDA–bitstream configuration, including bitstream generation, compression,...