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  1. No Access

    Chapter

    Introduction

    Much as the development of steel girders suddenly freed skyscrapers to reach beyond the 12-story limit of masonry buildings 6, achievements in four key processes have allowed the concept of 3D integrated circu...

    Kerry Bernstein in Three Dimensional Integrated Circuit Design (2010)

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    Chapter

    Thermal and Power Delivery Challenges in 3D ICs

    Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it ...

    Pulkit Jain, **qiang Zhou, Chris H. Kim… in Three Dimensional Integrated Circuit Design (2010)

  3. No Access

    Chapter

    Thermal-Aware 3D Placement

    Three-dimensional IC technology enables an additional dimension of freedom for circuit design. Challenges arise for placement tools to handle the through-silicon via (TS via) resource and the thermal problem, ...

    Jason Cong, Guojie Luo in Three Dimensional Integrated Circuit Design (2010)

  4. No Access

    Chapter

    Three-Dimensional Microprocessor Design

    Three-dimensional integration provides many new exciting opportunities for computer architects. There are many potential ways to apply 3D technology to the design and implementation of microprocessors. In this...

    Gabriel H. Loh in Three Dimensional Integrated Circuit Design (2010)

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    Chapter

    PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers

    With power and cooling increasingly contributing to the operating costs of a datacenter, energy efficiency is the key driver in server design. One way to improve energy efficiency is to implement innovative in...

    Taeho Kgil, David Roberts, Trevor Mudge in Three Dimensional Integrated Circuit Design (2010)

  6. No Access

    Chapter

    System-Level 3D IC Cost Analysis and Design Exploration

    The majority of the existing 3D IC research has focused on how to take advantage of the performance, power, smaller form-factor, and heterogeneous integration benefits offered by 3D integration. However, all s...

    **angyu Dong, Yuan **e in Three Dimensional Integrated Circuit Design (2010)

  7. No Access

    Chapter

    3D Process Technology Considerations

    Both form-factor and performance-scaling trends are driving the need for 3D integration, which is now seeing rapid commercialization. While overall process integration schemes are not yet standardized across t...

    Albert M. Young, Steven J. Koester in Three Dimensional Integrated Circuit Design (2010)

  8. No Access

    Chapter

    Thermal-Aware 3D Floorplan

    Three-dimensional integration makes floorplanning a much more difficult problem because the multiple device layers dramatically enlarge the solution space and the increased power density accentuates the therma...

    Jason Cong, Yuchun Ma in Three Dimensional Integrated Circuit Design (2010)

  9. No Access

    Chapter

    Thermal Via Insertion and Thermally Aware Routing in 3D ICs

    Thermal challenges in 3D chips motivate the need for on-chip thermal conduction networks to deliver the heat to the heat sink. The most prominent example is a passive network of thermal vias, which serves the ...

    Sachin S. Sapatnekar in Three Dimensional Integrated Circuit Design (2010)

  10. No Access

    Chapter

    Three-Dimensional Network-on-Chip Architecture

    On-chip interconnects are predicted to be a fundamental issue in designing multi-core chip multiprocessors (CMPs) and system-on-chip (SoC) architectures with numerous homogeneous and heterogeneous cores and fu...

    Yuan **e, Narayanan Vijaykrishnan, Chita Das in Three Dimensional Integrated Circuit Design (2010)

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    Chapter

    Wafer-Bonding Technologies and Strategies for 3D ICs

    Shari Farrens in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    3D Integration Based upon Dielectric Adhesive Bonding

    Jian-Qiang Lu, Timothy S. Cale, Ronald J. Gutmann in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    Cu Wafer Bonding for 3D IC Applications

    Kuan-Neng Chen, Chuan Seng Tan, Andy Fan… in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    3D Memory

    Robert S. Patti in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    An SOI-Based 3D Circuit Integration Technology

    James Burns, Brian Aull, Robert Berger… in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    Thermal Challenges of 3D ICs

    Sheng-Chih Lin, Kaustav Banerjee in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    Overview of Wafer-Level 3D ICs

    Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    Stacked CMOS Technologies

    Mansun Chan in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies

    Sharath Hosali, Greg Smith, Larry Smith… in Wafer Level 3-D ICs Process Technology (2008)

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    Chapter

    Direct Hybrid Bonding

    Bart Swinnen, Anne Jourdain, Piet De Moor… in Wafer Level 3-D ICs Process Technology (2008)

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