SpringerLink
Log in

Ultra-Low-Voltage Memory Circuits

  • Chapter
VLSI Memory Chip Design

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 5))

  • 1157 Accesses

Abstract

The reduction of the operating voltage is essential not only to reduce power dissipation, but also to ensure reliablity for miniaturized devices. Further reduction of the supply voltage allows users to design ultra-low-power systems or battery-based mobile equipment. One target is 0.9 V, the minimum voltage of a NiCd cell. Even in this case, higher performance will eventually be required, due to the ever-increasing demand for digital signal processing capability. To simultaneously achieve low voltage and high-speed operation, both device miniaturization and threshold voltage (V T) scaling are indispensable. Fortunately, the state-of-the-art device technology in miniaturization has at last progressed to the extent of realizing quite high speed even at low voltages of less than 2 V. Even SOI CMOS technology — more suitable for ultra-low-voltage operations — is being intensively developed. V T scaling, however, is highlighted as an emerging issue, because the reduction of V T increases the MOSFET subthreshold current [8.1–8.6], even in CMOS chips. The resulting dc current eventually dominates even the active chip current, losing the low-power advantage of CMOS circuits that we take for granted today. today. The issue is essential not only for the design of large-capacity RAM chips with a feature size of 0.1µm or less in the future, but also for the design of ultralow-voltage LSIs such as medium memory-capacity RAM chips and MPU chips with an existing fabrication process tailored to scaled V T.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Subscribe and save

Springer+ Basic
EUR 32.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or Ebook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
EUR 29.95
Price includes VAT (Germany)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
EUR 171.19
Price includes VAT (Germany)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
EUR 219.98
Price includes VAT (Germany)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free ship** worldwide - see info
Hardcover Book
EUR 235.39
Price includes VAT (Germany)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free ship** worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).

    Google Scholar 

  2. K. Itoh et al., Proc. IEEE 83(4), 524 (1995).

    Article  Google Scholar 

  3. K. Itoh, “Low power memory design”, in Low Power Design Methodologies, J.M. Rabaey, M. Pedram, Eds., Kluwer, Norwell, MA, pp. 201–251, Oct. 1995.

    Chapter  Google Scholar 

  4. K. Itoh et al., IEEE J. Solid-State Circuits 32, 624 (1997).

    Article  Google Scholar 

  5. K. Itoh, “Ultralow-Voltage Memory Circuits”, VLSI’97 Tutorial, Gramado (Brazil), Aug. 1997.

    Google Scholar 

  6. K. Itoh et al., Electrochem. Soc. Proc. 98–1, 350 (1998).

    Google Scholar 

  7. V.P. Tsividis, Operation and modeling of the MOS transistor (McGraw-Hill, New York 1998).

    Google Scholar 

  8. S.M. Sze, Physics of semiconductor devices (2 nd ed.) (John Wiley, New York 1981).

    Google Scholar 

  9. F.H. Gaensslen, R.C. Jaeger, “Low temperature microelectronics”, Ext. Abstr., 22 nd Conf. Solid State Devices and Materials, pp. 353–356, Aug. 1990.

    Google Scholar 

  10. W.H. Henkels et al., IEEE J. Solid-State Circuits 26(11), 1519 (1991).

    Article  Google Scholar 

  11. M. Aoki et al., IEEE Trans. Electron. Devices, 36(8), 1429 (1989).

    Article  Google Scholar 

  12. J.-P. Colinge IEEE Electron Device Lett. 7(4), 244 (1986).

    Article  Google Scholar 

  13. M. Aoki et al., “A 1.5 V DRAM for battery-based applications”, ISSCC Dig. Tech. Papers, pp. 238–239, Feb.1989.

    Google Scholar 

  14. Y. Nakagome et al., “A 1.5 V circuit technology for 64 Mb DRAMs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 17–18, June 1990.

    Google Scholar 

  15. G. Kitsukawa et al., IEEE J. Solid-State Circuits 28(11), 1105 (1993).

    Article  Google Scholar 

  16. M. Horiguchi et al., “Switched-source-impedance CMOS circuit for low standby current giga-scale LSIs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 47–48, May 1993.

    Google Scholar 

  17. T. Sakata et al., “Subthreshold-current reduction circuits for multi-gigabit DRAMs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 83–84, May 1993.

    Google Scholar 

  18. D. Takasima et al., “Stand-by/active mode logic for sub-l V l G/4 Gb DRAMs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 83–84, May 1993.

    Google Scholar 

  19. S. Mutoh et al., “1V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS”, IEEE ASIC Conf. Dig. Tech. Papers, pp. 186–189, Sept. 1993.

    Google Scholar 

  20. K. Seta et al., “50% active-power saving without speed degradation using stand-by power reduction (SPR) circuit”, ISSCC Dig. Tech. Papers, pp. 318–319, Feb. 1995.

    Google Scholar 

  21. D. Burnett et al., “Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits”, Symp. VLSI Technol. Dig. Tech. Papers, pp. 15–16, 1994.

    Google Scholar 

  22. N. Rohrer et al., “A 480 MHz RISC Microprocessor in a 0.12 μm Leff CMOS technology with copper interconnects”, ISSCC Dig. Tech. Papers, pp. 240–241, Feb. 1998.

    Google Scholar 

  23. K. Itoh, IEEE J. Solid-State Circuits 25(3), 778 (1990).

    Article  Google Scholar 

  24. Y. Nakagome et al., “Sub-1 V swing bus architecture for future low-power ULSIs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 82–83, June 1992.

    Google Scholar 

  25. Yibin Ye et al., “A new technique for standby leakage reduction in high-performance circuits”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 40–41, 1998.

    Google Scholar 

  26. M. Hasegawa et al., “A 256 Mb SDRAM with subthreshold leakage current suppression”, ISSCC Dig. Tech. Papers, pp. 80–81, Feb. 1998.

    Google Scholar 

  27. T. Sakata et al., IEEE Solid-State Circuits 29(8), 887 (1994).

    Article  Google Scholar 

  28. H. Akamatsu et al., “A low power data holding circuit with an intermittent power supply scheme for sub-1 V MT-CMOS LSIs”, Symp. VLSI Crircuits Dig. Tech. Papers, pp. 14–15, June 1996.

    Google Scholar 

  29. T. Kuroda et al., “A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme”, ISSCC Dig. Tech. Papers, pp. 166–167, Feb. 1996.

    Google Scholar 

  30. M. Mizuno et al., “Elastic-V t CMOS circuits for multiple on-chip power control”, ISSCC Dig. Tech. Papers, pp. 300–301, Feb. 1996.

    Google Scholar 

  31. K. Kumagai et al., “A novel power-down scheme for low V T CMOS circuits”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 44–45, 1998.

    Google Scholar 

  32. H. Makino et al., “An auto-backgate-controlled MT-CMOS circuit”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 42–43, 1998.

    Google Scholar 

  33. T. Ooishi et al., “A well-synchronized sensing/equalizing method for sub- 1.0 V operating advanced DRAMs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 81–82, May 1993.

    Google Scholar 

  34. L.S.Y. Wong, G.A. Rigby, “A 1 V CMOS digital circuit with double-gate-driven MOSFET”, ISSCC Dig. Tech. Papers, pp. 292–293, Feb. 1997.

    Google Scholar 

  35. T. Kawahara et al., IEEE J. Solid-State Circuits 26(11), 1530 (1991).

    Article  Google Scholar 

  36. K. Ishibashi et al., “A 1 V TET-load SRAM using a two-step word-voltage method”, ISSCC Dig. Tech. Papers, pp. 206–207, Feb. 1992.

    Google Scholar 

  37. K. Ishibashi et al., IEEE J. Solid-State Circuits 30, 480 (1995).

    Article  Google Scholar 

  38. H. Morimura et al., IEEE J. Solid-State Circuits 33(8), 1220 (1998).

    Article  Google Scholar 

  39. H. Mizuno et al., “Driving source-line (DSL) cell architecture for sub-1 V high-speed low-power applications”, Symp. VLSI Circuits. Dig. Tech. Papers, pp. 25–26, June 1995.

    Google Scholar 

  40. H. Yamaguchi et al., “A 0.8 V/100 MHz/Sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme”, Symp. VLSI Circuits. Dig. Tech. Papers, pp. 126–127, June 1996.

    Google Scholar 

  41. K. Itoh et al., “A deep sub-V, single power-supply SRAM cell with multi- V t, boosted storage node and dynamic load”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 132–133, June 1996.

    Google Scholar 

  42. H. Kawaguchi et al., “Dynamic leakage cut-off scheme for low-voltage SRAMs”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 140–141, June 1998.

    Google Scholar 

  43. Y. Yamaguchi et al., IEICE Trans. Electron. E79-C, 772 (1996).

    Google Scholar 

  44. C. Chuang et al., Proc.IEEE 86(4), 689 (1998).

    Article  CAS  Google Scholar 

  45. Y. Yamaguchi et al., IEICE Trans. Electron. E78-C, 812 (1995).

    Google Scholar 

  46. K. Ueda et al., “A CAD-compatible SOI/CMOS gate array having body-fixed partially-depleted transistors”, ISSCC Dig. Tech. Papers, pp. 288–289, Feb. 1997.

    Google Scholar 

  47. K. Shimomura et al, “A 1 V 46 ns 16 Mb SOI-DRAM with body control technique”, ISSCC Dig. Tech. Papers, pp. 68–69, Feb. 1997.

    Google Scholar 

  48. S. Kuge et al., “SOI-DRAM circuit technologies for low power high speed multi-giga scale memories”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 103–104, 1995.

    Google Scholar 

  49. F. Assaderaghi et al., “A novel silicon-on-insulator (SOI) MOSFET for ul- tralow voltage operation”, Symp. Low Power Electronics Dig. Tech. Papers, pp. 58–59, 1994.

    Google Scholar 

  50. T. Fuse et al., “A 0.5 V 200 MHz 1-stage 32b ALU using a body bias controlled SOI pass-gate logic”, ISSCC Dig. Tech. Papers, pp. 286–287, Feb. 1997.

    Google Scholar 

  51. T. Douseki et al., “A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate”, ISSCC Dig. Tech. Papers, pp. 84–85, Feb. 1996.

    Google Scholar 

  52. F. Morishita et al., “Leakage mechanism due to floating body and coun- termeasure on dynamic retention mode of SOI-DRAM”, Symp. VLSI Tech. Dig. Tech. papers, pp. 141–142, 1995.

    Google Scholar 

  53. T. Tanigawa et al., IEICE Trans. Electron. E79-C, 781 (1996).

    Google Scholar 

  54. S. Tomishima et al., “A long data retention SOI-DRAM with the body refresh function”, Symp. VLSI Circuits Dig. Tech. Papers, pp. 198–199, June 1996.

    Google Scholar 

  55. Y. Tosaka et al., IEICE Trans. Electron. E79-C, 767 (1996).

    Google Scholar 

  56. B.S. Amrutur et al., “Techniques to reduce power in fast wide memories”, Symp. Low Power Electronics Dig. Tech. Papers, pp. 92–93, Oct. 1994.

    Google Scholar 

  57. B.S. Amrutur, M.A. Horowitz, “A replica technique for wordline and sense control in low-power SRAMs”, IEEE J. Solid-State Circuits, 33(8), 1208 (1998).

    Article  Google Scholar 

  58. T. Hamamoto et al., “Well conception: a novel scaling limitation factor derived from DRAM retention time and its modeling”, IEDM Dig. Tech. Papers, pp. 915–918, Dec. 1995.

    Google Scholar 

  59. Y. Nakagome et al., IEEE J. Solid-State Circuits 26(7), 1003 (1991).

    Article  Google Scholar 

  60. R. Khanna et al., “A 0.25 um X86 microprocessor with a 100 MHz Socket 7 Interface”, ISSCC Dig. Tech. Papers, pp. 242–243, Feb. 1998.

    Google Scholar 

  61. G. Singh, “A high speed 3.3 V IO Buffer with 1.9 V tolerant CMOS process”, European Solid-State Circuits Conference Dig. Tech. Paper, pp. 128–131, Sept. 1998.

    Google Scholar 

  62. H. Mizuno et al., “A 18 μA-stanby-current 1.8 V 200 MHz microprocessor with self substrate-biased data retention mode”, ISSCC Dig. Tech. Papers, pp. 280–281, Feb. 1999.

    Google Scholar 

  63. M. Miyazaki et al., “A 1000 MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias”, ISSCC Dig. Tech. Papers, pp. 420–421, Feb. 2000.

    Google Scholar 

  64. O. Takahashi et al., “1 GHz fully pipelined 3.7 ns address access time k x 1024 embedded DRAM macro”, ISSCC Dig. Tech. Papers, pp. 396–397, Feb. 2000.

    Google Scholar 

  65. A.H. Montree et al., “Limitations to adaptive back bias approach for standby power reduction in deep sub-micron CMOS”, ESSDERC Proc, pp. 580–583, Sept. 1990.

    Google Scholar 

  66. K. Itoh et al., “VLSI memory technology: current status and future trends”, ESSCIRC Dig. Tech. Papers, pp. 3–10, Sept. 1999.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Central Research Laboratory, Hitachi Ltd., 1-280, Higashi-Koigakubo, Kokubunji-shi, Tokyo, 185-8601, Japan

    Dr. Kiyoo Itoh

Authors
  1. Dr. Kiyoo Itoh
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Itoh, K. (2001). Ultra-Low-Voltage Memory Circuits. In: VLSI Memory Chip Design. Springer Series in Advanced Microelectronics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-04478-0_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-662-04478-0_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-08736-3

  • Online ISBN: 978-3-662-04478-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation