SpringerLink
Log in

On-Chip Voltage Generators

  • Chapter
VLSI Memory Chip Design

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 5))

  • 1301 Accesses

Abstract

On-chip voltage generation [5.1–5.8] is becoming increasingly important for memory LSI design, as well as for other LSI designs. This importance is being accelerated by a recent trend toward lower-voltage operation. In the past, generators have been widely used in commercial memory chips such as DRAMs and Flash memories, as explained in Chap. 1. For example, DRAM chips have needed various kinds of power-supply voltages, which have been generated internally by using a single external supply-voltage (V DD), as shown in Fig. 5.1. A negative voltage (V BB) is a substrate bias voltage supplied to an NMOS memory-cell array to ensure stable memory-cell operation. A boosted dc voltage (V DH or V PP) is for word bootstrap**, to eliminate the drop in the cell V T. A half-V DD (or V DL) achieves a half-V DD (or V DL) data-line précharge for power reduction, and a half-V DD (or V DL) cell-capacitor plate for high S/N ratio design, as explained in Chaps. 3 and 4. Modern commercial DRAMs of 16 Mb and beyond even incorporate an on-chip voltage down-converter, which lowers V DD to V DL, by using an internal reference voltage (V REF), to simultaneously achieve high reliability of small devices and power-supply standardization. Flash memories have also used an extremely boosted word-line voltage, and even a negative voltage, to relaxing a stress voltage to a memory-cell FET, as explained in Chap. 1. Schematic circuits for generating these internal voltages are shown in Fig. 5.2.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Subscribe and save

Springer+ Basic
EUR 32.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or Ebook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 179.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 229.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free ship** worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free ship** worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).

    Google Scholar 

  2. K. Itoh et al., Proc. IEEE 83(4), 524 (1995).

    Article  Google Scholar 

  3. K. Itoh et al., IEEE J. Solid-State Circuits 32(5), 624 (1997).

    Article  Google Scholar 

  4. K. Itoh, “Ultralow-voltage memory circuits”, VLSI’97 Tutorial, Gramado (Brazil), 1997.

    Google Scholar 

  5. R.D. Pashley, A. McCormick, “A 70 ns 1 K MOS RAM”, ISSCC Dig. Tech. Papers, pp. 138–139, Feb. 1976.

    Google Scholar 

  6. K. Itoh et al., “A single 5 V-only 64 K dynamic RAM”, ISSCC Dig. Tech. Papers, pp. 228–229, Feb. 1980.

    Google Scholar 

  7. H. Masuda et al., IEEE J. Solid-State Circuits SC-15(5), 846 (1980).

    Article  Google Scholar 

  8. W.L. Martino et al., IEEE J. Solid-State Circuits SC-15(5), 820 (1980).

    Article  Google Scholar 

  9. T. Kuroda et al., “A 0.9 V 150 MHz 10 mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme”, ISSCC Dig. Tech. Papers, pp. 166–167, Feb. 1996.

    Google Scholar 

  10. T. Furuyama et al., “A latch-up like new failure mechanism for high density CMOS dynamic RAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 33–34, May 1989.

    Google Scholar 

  11. M. Hasegawa et al., “A 256 Mb SDRAM with subthreshold leakage current suppression”, ISSCC Dig. Tech. Papers, pp. 80–81, Feb. 1998.

    Google Scholar 

  12. K. Shimotori et al., IECE J64-C(11), 769 (1981).

    Google Scholar 

  13. M.I. Elmasry, Digital MOS integrated circuits, p. 23 (IEEE Press, New York 1981).

    Google Scholar 

  14. Miyamoto et al., IECE J75-C-II(1), 38 (1992).

    Google Scholar 

  15. D. Takacs et al., “Static and transient latch-up hardness in n-well CMOS with on-chip substrate bias generator”, IEDM 85 Dig. Tech. Papers, pp. 504–508, 1985.

    Google Scholar 

  16. Taniguchi et al., IECE J65-C(7), 530 (1982).

    Google Scholar 

  17. E. Takeda et al., “Hot-carrier effects in submicron VLSIs”, Symp. VLSI Technol., Dig. Tech. Papers, pp. 104–105, 1983.

    Google Scholar 

  18. E. Takeda et al., IEEE Trans. Electron Devices ED-29(4), 611 (1982).

    Article  Google Scholar 

  19. T. Horiuchi et al., “Hot-carrier induced degradation of N-MOSFETS in inverter operation”, Symp. VLSI Technol., Dig. Tech. Papers, pp. 104–105, 1985.

    Google Scholar 

  20. S. Ogura et al., IEEE Trans. Electron Devices ED-27(8), 1359 (1980).

    Article  Google Scholar 

  21. T. Sakurai et al, IEEE J. Solid-State Circuits SC-21(1), 187 (1986).

    Article  Google Scholar 

  22. J. Harter et al., “A 60 ns hot electron resistant 4 M DRAM with trench cell”, ISSCC88 Dig. Tech. Papers, pp. 244–245, Feb. 1988.

    Google Scholar 

  23. K. Nogami et al., “VLSI circuit reliability under ac hot-carrier stress”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 13–14, May 1987.

    Google Scholar 

  24. K. Furutani et al., IEICE Trans. J73-C-II(5), 302 (1990).

    Google Scholar 

  25. T. Nakano, Y. Akasaka, “ULSI DRAM technology (in Japanese)”, Science Forum, Sept. 1992.

    Google Scholar 

  26. S. Kohyama et al., “Non-thermal carrier generation in MOS structures”, 11th Conf. Solid-State Devices — Tokyo, p. A-2–2, 1979.

    Google Scholar 

  27. A. Mohsen et al., IEEE J. Solid-State Circuits SC-19(5), 610 (1984).

    Article  Google Scholar 

  28. C. Webb et al., “A 65 ns CMOS 1 Mb DRAM”, ISSCC Dig. Tech. Papers, pp. 262–263, Feb. 1986.

    Google Scholar 

  29. S. Fujii et al., IEEE J. Solid-State Circuits 24(5), 1170 (1989).

    Article  Google Scholar 

  30. K. Sato et al, “A 20 ns static column 1 Mb DRAM in CMOS technology”, ISSCC Dig. Tech. Papers, pp. 254–255, Feb. 1985.

    Google Scholar 

  31. Y. Konishi et al., IEEE J. Solid-State Circuits 25(5), 1112 (1990).

    Article  Google Scholar 

  32. Y. Tsukikawa et al., “An efficient back-bias generator with hybrid pum** circuit for 1.5 V DRAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 85–86, 1993.

    Google Scholar 

  33. T. Mano et al., “Submicron VLSI memory circuits”, ISSCC83 Dig. Tech. Papers, pp. 234–235, Feb. 1983.

    Google Scholar 

  34. K. Itoh et al., “An experimental 1 Mb DRAM with on-chip voltage limiter”, ISSCC84 Dig. Tech. Papers, pp. 282–283, Feb. 1984.

    Google Scholar 

  35. K. Itoh, IEEE J. Solid-State Circuits 25(3), 778 (1990).

    Article  Google Scholar 

  36. K. Itoh, “Reviews and prospects of deep sub-micron DRAM technology”, Int. Conf. Solid State Devices and Materials, Ext. Abstr., pp. 468–471, Aug. 1991.

    Google Scholar 

  37. M. Aoki et al., “A 1.5 V DRAM for battery-based applications”, ISSCC89 Dig. Tech. Papers, pp. 238–239, Feb. 1989.

    Google Scholar 

  38. Y. Nakagome et al, IEEE J. Solid-State Circuits 26(4), 465 (1991).

    Article  Google Scholar 

  39. K. Sato et al., IEEE J. Solid-State Circuits 26(11), 1556 (1991).

    Article  Google Scholar 

  40. H. Hidaka et al,, IEEE J. Solid-State Circuits 27(7), 1020 (1992).

    Article  Google Scholar 

  41. R.S. Mao et al., “A new on-chip voltage regulator for high density CMOS DRAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 108–109, 1992.

    Google Scholar 

  42. Y. Nakagome et al., IEEE J. Solid-State Circuits, 26(7), 1003 (1991).

    Article  Google Scholar 

  43. T. Furuyama et al., “An experimental 4 Mb CMOS DRAM”, ISSCC86 Dig. Tech. Papers, pp. 272–273, Feb. 1986.

    Google Scholar 

  44. T. Furuyama et al., IEEE J. Solid-State Circuits, SC-22(3), 437 (1987).

    Article  Google Scholar 

  45. D. Chin et al., IEEE J. Solid-State Circuits 24(5), 1191 (1989).

    Article  Google Scholar 

  46. M. Horiguchi et al., IEEE J. Solid-State Circuits 23(5), 1128 (1988).

    Article  Google Scholar 

  47. M. Horiguchi et al, IEEE J. Solid-State Circuits, 25(5), 1129 (1990).

    Article  Google Scholar 

  48. M. Horiguchi et al., IEEE J. Solid-State Circuits, 26(11), 1544 (1991).

    Article  Google Scholar 

  49. D.S. Min et al, IEEE J. Solid-State Circuits 27(4), 626 (1992).

    Article  Google Scholar 

  50. M. Takada et al., “A 4 Mb DRAM with half internal voltage bit line precharge”, ISSCC86 Dig. Tech. Papers, pp. 270–271, Feb. 1986.

    Google Scholar 

  51. A. Tanbe et al., IEEE J. Solid-State Circuits 27(11), 1525 (1992).

    Article  Google Scholar 

  52. D. Takashima et al., IEEE J. Solid-State Circuits 27(4), 603 (1992).

    Article  Google Scholar 

  53. H. Tanaka et al., IEICE Trans. Electron. E75-C(11), 1333 (1992).

    Google Scholar 

  54. P.R. Gray, R.G. Meyer, Analysis and design of analog integrated circuits, 2 nd ed. (John Wiley, New York).

    Google Scholar 

  55. H. Tanaka et al., IEICE Trans. J75-C-2(8), 425 (1992).

    Google Scholar 

  56. Nakamura et al., “Study of the relation of internal voltage converter and ground noise”, Proc. IEICE Spring Conf., Part 5, C-618, 1993.

    Google Scholar 

  57. G. Kitsukawa et al., IEEE J. Solid-State Circuits 24(3), 597 (1989).

    Article  Google Scholar 

  58. P.E. Allen, D.R. Holberg, CMOS analog circuit design (Holt, Rinehart and Winston, New York).

    Google Scholar 

  59. S.M. Yoo et al., IEEE J. Solid-State Circuits 28(4), 499 (1993).

    Article  Google Scholar 

  60. R.A. Blauschild et al., IEEE J. Solid-State Circuits SC-13(6), 767 (1978).

    Article  Google Scholar 

  61. H. Tanaka et al., “Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 87–88, May 1993.

    Google Scholar 

  62. Tsuruda et al., “A tuning method of voltage down converter circuit”, Proc. IEICE Spring Conf., Part 5, C-643, 1993.

    Google Scholar 

  63. R.C. Foss et al., “Application of a high-voltage pumped supply for low-power DRAM”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 106–107, 1992.

    Google Scholar 

  64. D. Lee et al., “A 35 ns 64 Mb DRAM using on-chip boosted power supply”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 64–65, 1992.

    Google Scholar 

  65. H. Miyamoto et al., “A 32 ns 64 Mb DRAM with extended second metal line architecture”, ESSCIRC93 Dig. Tech. Papers, pp. 41–44, Sept. 1993.

    Google Scholar 

  66. S. Fujii et al., “A 50 μA standby 1 MW lb/256 KW 4b CMOS DRAM”, ISSCC86 Dig. Tech. Papers, pp. 266–267, Feb. 1986.

    Google Scholar 

  67. A.L. Roberts et al., “A 256 K SRAM with on-chip power supply conversion”, ISSCC Dig. Tech. Papers, pp. 252–253, Feb. 1987.

    Google Scholar 

  68. K. Ishibashi et al., IEEE J. Solid-State Circuits 27(6), 920 (1992).

    Article  Google Scholar 

  69. H.J. Shin et al., “Low-dropout on-chip voltage regulator for low-power circuits”, IEEE Symp. Low Power Electronics, Dig., pp. 76–77, 1994.

    Google Scholar 

  70. G.W. den Besten, B. Nauta, IEEE J. Solid-State Circuits 33(7), 956 (1998).

    Article  Google Scholar 

  71. T. Ooishi et al., “A mixed-mode voltage-down converter with impedance adjustment circuitry for low-voltage wide-frequency DRAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 111–112, June 1995.

    Google Scholar 

  72. H. Neuteboom et al, IEEE J. Solid-State Circuits 32(11), 1790 (1997).

    Article  Google Scholar 

  73. Y. Nakagome, “Voltage regulator design for low voltage DRAMs”, Symp. VLSI Circuits, Memory Design Short Course, June 1998.

    Google Scholar 

  74. P. Favrat et al, IEEE J. Solid-State Circuits 33(3), 410 (1998).

    Article  Google Scholar 

  75. T. Hamamoto et al., “An efficient charge recycle and transfer pump circuit for low operating voltage DRAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 110–111, June 1996.

    Google Scholar 

  76. H. Tanaka et al, IEEE J. Solid-State Circuits 34(8), 1084 (1999).

    Article  Google Scholar 

  77. H. Mizuno et al, “A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode”, ISSCC Dig. Tech. Papers, pp. 280–281, Feb. 1999.

    Google Scholar 

  78. M. Miyazaki et al., “A 1000-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias”, ISSCC Dig. Tech. Papers, pp. 420–421, Feb. 2000.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Central Research Laboratory, Hitachi Ltd., 1-280, Higashi-Koigakubo, Kokubunji-shi, Tokyo, 185-8601, Japan

    Dr. Kiyoo Itoh

Authors
  1. Dr. Kiyoo Itoh
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Itoh, K. (2001). On-Chip Voltage Generators. In: VLSI Memory Chip Design. Springer Series in Advanced Microelectronics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-04478-0_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-662-04478-0_5

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-08736-3

  • Online ISBN: 978-3-662-04478-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation