Abstract
Several essential inventions and innovations, and subsequent sustained efforts [1.1] toward high densities have paved the way to large-scale integrated circuit (LSI) memories, as shown in Fig. 1.1 [1.2]. Since two epoch-making announcements accompanying the start of LSI memory production in 1970 [the first extensive usage of a semiconductor memory chip for the IBM 370 mainframe computers, and the first sales of a 1-Kb dynamic random access memory (DRAM), named the 1103, from Intel], the increase in memory chip capacity has skyrocketed with the help of the ever-higher-density MOS/CMOS design and technology. The resultant LSI memories have given computers, networks, and almost everything with electrical components the benefit of a dramatically reduced cost per bit and far superior performance. Data processors and data terminals, such as personal computers, workstations, and POS terminals, as well as telephone exchanges, digital televisions, and numerical control machines, could not have been produced without them.
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References
L.M. Terman, “Memory at ISSCC”, ISSCC Commemorative Supplement to the Digest of Technical Papers, pp. 91–111, Feb. 1993.
H. Sunami, “Co** with Memory-Cell Miniaturization by Using New Materials”, Nikkei Microdevices, pp. 144–157, Dec. 1997.
T. Murotani et al., “A 4-Level Storage 4 Gb DRAM”, ISSCC Dig. Tech. Papers, pp. 74–75, Feb. 1997.
R.H. Dennard, “Field-Effect Transistor Memory”, U.S. Patent 3387286, June 4, 1968.
F.M. Wanlass, CT. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes”, ISSCC Dig. Tech. Papers, pp. 32–33, Feb. 1963.
D.F. Benchkowsky, “A Fully-Decoded 2048-bit Electrically-Programmable MOS ROM”, ISSCC Dig. Tech. Papers, pp. 80–81, Feb. 1971.
Nikkei Electronics, No. 694, pp. 83–102, July 14, 1997.
Final Worldwide Semiconductor Market Share, 1995 and 1998, and Worldwide Memory Market Share, 1993 to 1995, Dataquest.
K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).
Calculated with data for 64 Mb DRAMs presented at ISSCC91, ISSCC92, ESSCIRC 92 and ESSCIRC 93.
Calculated with data for a 16 Mb CMOS SRAM presented at ISSCC 92.
T. Takeshima et al., “A 3.3 V Single-Power-Supply 64 Mb Flash Memory with Dynamic Bit-Line Latch Programming Scheme”, ISSCC Dig. Tech. Papers, pp. 148–149, Feb. 1994.
H.K. Burke, G.J. Michon, “Charge Pump Random-Access Memory”, ISSCC Dig. Tech. Papers, pp. 16–17, Feb. 1972.
W. Martino, B.F. Croxon, “The Inverting Cell Concept for MOS Dynamic RAMs”, ISSCC Dig. Tech. Papers, pp. 12–13, Feb. 1972.
W.M. Regitz, J. Karp, “A Three-Transistor-Cell, 1024- Bit, 500 NS MOS-RAM”, ISSCC Dig. Tech. Papers, pp. 42–43, Feb. 1970.
J.A. Karp et al., “A 4096- Bit Dynamic MOS RAM”, ISSCC Dig. Tech. Papers, pp. 10–11, Feb. 1972.
K. Itoh, IEEE J. Solid-State Circuits 25(3), 778 (1990).
T. Masuhara et al., IEICE Trans. E74(1), 130 (1991).
Y. Nakagome, K. Itoh, IEICE Trans. E74(4), 779 (1991).
K. Itoh, “Reviews and Prospects of Deep Sub-Micron DRAM Technology”, SSDM91, Extended Abstracts, pp. 468–471, Aug. 1991.
K. Itoh et al., IEEE Proc. 83(4), 524 (1995).
K. Itoh et al., IEEE J. Solid-State Circuits 32(5), 624 (1997).
K. Itoh, “Ultralow-Voltage Memory Circuits”, VLSI’97, Tutorial, Gramado (Brazil), Aug. 1997.
K. Itoh et al., Electrochem. Soc. Proc. 98(1), 350 (1998).
H. Masuda et al., IEEE Trans. Electron. Devices ED-27(8), 1607 (1980).
H. Masuda et al., IEEE J. Solid-State Circuits SC-15(5), 846 (1980).
Y. Kawamoto et al., “A 1.28 μm2 bit-line shielded memory cell technology for 64 Mb DRAMs”, Symp. VLSI Technol. Dig. Tech. Papers, pp. 13–14, June 1990.
Y. Nakagome et al., IEEE J. Solid-State Circuits 26(4), 465 (1991).
M. Takada, T. Enomoto, IEICE Trans. E74(4), 827 (1991).
K. Ishibashi, IEICE Trans. E79-C(6) 724 (1996).
M. Minami et al., “A 6.93-μm2 n-Gate Full CMOS SRAM Cell Technology with High-performance 1.8 V Dual-Gate CMOS for Peripheral Circuits”, Symp. VLSI Technol. Dig. Tech. Papers, pp. 13–14, June 1995.
K. Ishibashi et al., “A 300 MHz 4 Mb Wave-Pipeline CMOS SRAM Using a Multi-Phase PLL”, ISSCC Dig. Tech. Papers, pp. 308–309, Feb. 1995.
F. Masuoka et al., “A New Flash EEPRO M Cell using Triple Polysilicon Technology”, IEDM Tech. Dig., pp. 464–467, Dec. 1984.
F. Masuoka et al., IEICE Trans. E74(4), 868 (1991).
P. Pavan et al., IEEE Proc. 85(8), 1248 (1997).
H. Kume, Oyo Buturi 65(11), 1114, (1996) (in Japanese).
V.N. Kynett et al., “An in-system reprogrammable 256 K CMOS Flash memory”, ISSCC Dig. Tech. Papers, pp. 132–133, Feb. 1988.
S. Haddad et al., Electron Device Letters, 11(11), 514 (1990).
F. Masuoka et al., “New ultra high density EPRO M and Flash EEPRO M cell with NAND structure cell”, IEDM Dig. Tech. Papers, pp. 552–555, 1987.
H. Onoda et al., “Anovel cell structure suitable for a 3 V operation, sector erase FLASH memory”, IEDM Dig. Tech. Papers, pp. 599–602, 1992.
H. Kume et al., “A 1.28 μm2 contactless memory cell technology for a 3 V- only 64 Mbit EEPROM”, IEDM Dig. Tech. Papers, pp. 991–993, 1992.
M. Baur et al., “A Multilevel-Cell 32 Mb Flash Memory”, ISSCC Dig. Tech. Papers, pp. 132–133, Feb. 1995.
Nonvolatile Semiconductor Memory Technology, W.D. Brown, J.E. Brewer, Editors, IEEE PRESS, 1997.
K. Itoh et al., “VLSI Memory Technology: Current Status and Future Trends”, ESSCIRC’99 Dig. Tech. Papers, pp. 3–10, Sept. 1999.
Kirihata et al, “A 390 mm2 16 Bank 1 Gb DDR SDRAM with Hybrid Bitline Architecture”, ISSCC99 Dig. Tech. Papers, pp. 420–421, Feb. 1999.
S. Takase, N. Kushiyama, “A 1.6 GB/s DRAM with Flexible Map** Redundancy Technique and Additional Refresh Scheme”, ISSCC99 Dig. Tech. Papers, pp. 410–411, Feb. 1999.
O. Takahashi et al., “1 GHz Fully Pipelined 3.7 ns Address Access Time 8k × 1024 Embedded DRAM Macro”, ISSCC Dig. Tech. Papers, pp. 396–397, Feb. 2000.
H. Nambu et al., “A 550-ps Access, 900-MHz, 1- Mb ECL-CMOS SRAM”, Symp. VLSI Circuits, June 1999.
For example, SRAM chips in ISSCC Dig. Tech. Papers, Feb. 1999 and 2000.
A. Nozoe et al., “A 256 Mb Multilevel Flash Memory with 2 MB/s Program Rate for Mass Storage Applications”, ISSCC99 Dig. Tech. Papers, pp. 110–111, Feb. 1999.
K. Imamiya et al., “A 130 mm2 256 Mb NAND Flash with Shallow Trench Isolation Technology”, ISSCC99 Dig. Tech. Papers, pp. 112–113, Feb. 1999.
Byung-Gil Jeon et al, “A 0.4 μm 3.3 V 1T1C 4 Mb Nonvolatile Ferroelectric RAM with Fixed Bit-line Reference Voltage Scheme and Data Protection Circuit”, ISSCC Dig. Tech. Papers, pp. 272–273, Feb. 2000.
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Itoh, K. (2001). An Introduction to Memory Chip Design. In: VLSI Memory Chip Design. Springer Series in Advanced Microelectronics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-04478-0_1
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DOI: https://doi.org/10.1007/978-3-662-04478-0_1
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