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V FB /V TH Anomaly in High-k Gate Stacks

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High Permittivity Gate Dielectric Materials

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 43))

Abstract

One of the biggest challenges of metal/high-k gate stack technology is controlling the threshold voltage (V TH ) because achieving a high performance CMOS is almost impossible without it. We discuss anomalous V TH in poly-Si/high-k gate stacks and in metal/high-k systems. The possible origin for anomalous behavior is also discussed, focusing on the dipole formation difference between the top and bottom interfaces.

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Acknowledgments

We would like to thank collaboration members in The University of Tokyo (UT) and in the MIRAI project, particularly Koji Kita (UT) for his contribution to the bottom dipole formation model, and Masataka Hirose (MIRAI) for his useful discussion and continuous encouragement. This work was partly supported by a Grant-in-Aid for Scientific Research from MEXT in Japan and partly conducted in the MIRAI Project supported by NEDO.

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Authors and Affiliations

  1. The University of Tokyo, Tokyo, 113-8656, Japan

    Akira Toriumi

  2. National Institute for Materials Science, Tsukuba, 305-0044, Japan

    Toshihide Nabatame

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  1. Akira Toriumi
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  2. Toshihide Nabatame
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Correspondence to Akira Toriumi .

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Editors and Affiliations

  1. Dept. Electrical Engineering, Indian Institute of Technology, Kanpur, 208016, India

    Samares Kar

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Toriumi, A., Nabatame, T. (2013). V FB /V TH Anomaly in High-k Gate Stacks. In: Kar, S. (eds) High Permittivity Gate Dielectric Materials. Springer Series in Advanced Microelectronics, vol 43. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36535-5_6

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  • DOI: https://doi.org/10.1007/978-3-642-36535-5_6

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  • Print ISBN: 978-3-642-36534-8

  • Online ISBN: 978-3-642-36535-5

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