Abstract
This paper presents a SystemC cycle-accurate simulator, called REmulator, for a dynamically coarse-grained reconfigurable architecture template. By hierarchy modeling, REmulator can either be used at transaction-level, which benefits great for fast simulation of high-level hardware and embedded software, or at register transfer level, which can support more detailed evaluation outcomes on performance and power. In REmulator, the reconfigurable architecture template is described as a parameterized SystemC model so that it can be represented as different architecture schemes, and its architecture parameters would serve as input of the compiler back end, which allows rapid application map** with architecture modification. A case study on design space exploration of routing network and configuration compression in reconfigurable array demonstrates how exploration is used to adjust and optimize a better architecture template.
The work was sponsored by the National Scientific Foundation of China (Grant No. 61006029) and Jiangsu Scientific Foundation (Grant No. BK2010165).
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Chen, R., Ma, L., Yue, D., Wen, W., Qi, Z. (2011). Hierarchy Modeling and Co-simulation of a Dynamically Coarse-Grained Reconfigurable Architecture. In: Yang, D. (eds) Informatics in Control, Automation and Robotics. Lecture Notes in Electrical Engineering, vol 133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25992-0_80
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DOI: https://doi.org/10.1007/978-3-642-25992-0_80
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