Abstract
In most parallel algorithms, inter-processor communication cost is much more than computing cost within a processor. So, it is very important to reduce the amount of inter-processor communication. This paper presents the design and experiment of a new communication-aware parallel quicksort scheme for distributed-memory multiprocessor systems. The key idea of the proposed scheme is the weighted partition of processors, which enables not only less inter-processor communication but also better load balancing among the participating processors during the quicksort. The proposed scheme was designed and experimented on the Cray T3E parallel computer. According to the comparative performance measurement, for up to 64 processors, the proposed scheme results in about 40 60 percent shorter run time compared to the conventional parallel quicksort. That is mainly due to the small amount of inter-processor communication that results from the weighted partition and allocation of processors. The performance improvement is more substantial as the number of processors, the input size, and the input item size increases.
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Moh, S., Yu, C., Han, D. (2004). Design and Experiment of a Communication-Aware Parallel Quicksort with Weighted Partition of Processors. In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C.J.K., Gervasi, O. (eds) Computational Science and Its Applications – ICCSA 2004. ICCSA 2004. Lecture Notes in Computer Science, vol 3046. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24768-5_11
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DOI: https://doi.org/10.1007/978-3-540-24768-5_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22060-2
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