A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology

Abstract

This paper presents a 20 Gb/s receive equalizer including an adaptive continuous time linear equalizer (CTLE) and a 2-tap half-rate decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE can adjust the ratio of high frequency and low frequency components adaptively by detecting the energy at both ends of a slicer and then generating a control signal by an integrator. Following the CTLE is a half-rate DFE which can get a better trade-off between the working speed and design complexity especially for the case of 20 Gb/s or above. The chip area including pads and chip guarding is about 0.72 × 0.86 mm² and the power consumption is about 528 mW. Post simulation results show that the horizontal eye opening of the equalized data can be up to 0.9 UI at 20 Gb/s.

1 Introduction

The requirement of high data rate in wire-line communications has been becoming more and more intense. The chip-to-chip and board-to-board communication are moving towards 20 Gb/s or above. The channel loss, jitter, cross-talk and noise will become more and more serious with the increase of velocity [1,2,3]. In order to compensate channel loss or combat the inter-symbol interference, a variety of equalization schemes are widely used at the near or far end. Partial response maximum likelihood equalization based on sequence detection can find the most probable transmission sequence from all possible sequences and get the lowest bit error rate [4, 5]. Because the structure of Viterbi decoder is too complex, and difficult to implement with high speed circuit, it is seldom used in high speed serial link.

In the receiver, the feed forward equalizer (FFE) has a simple structure and can cancel pre-cursor ISI and post-cursor ISI simultaneously. At high speed, e.g. 20 Gb/s or beyond, it is difficult to design high precision delay line which is easily affected by the process, voltage, temperature (PVT) [6,7,8]. Similarly, the continuous time linear equalizer (CTLE) can also eliminate the pre-cursor and post-cursor by increasing the high-frequency components of the signal. But the noise and crosstalk is potentially amplified by the CTLE [9, 10]. DFE is a nonlinear structure and it is the most effective equalizer to eliminate the post-cursor. In order to eliminate the influence of the previous symbol on the current symbol, the previous symbol is fed back and subtracted from the current symbol. Since the feedback signals are hard decision signals, the feedback signals do not enhance crosstalk and noise. The structure of DFE equalizer is simple and easy to operate at relatively high rate [11,12,13,14].

The reminder of the paper is structured as follows. We review the principle of the adaptive CTLE based on the slope detection and the half-rate DFE. Then, the circuit design of the key modules is introduced in Sect. 3. We give the circuit layout and post-simulation results in Sect. 4. Finally, we draw conclusions in Sect. 5.

2 Architecture

The overall structure consists of an adaptive CTLE and a half-rate DFE, as shown in Fig. 1. Adaptive CTLE can provide high frequency gain and compensate the loss caused by channel bandwidth degradation. In addition, CTLE can not only make up for some of the shortcomings of DFE, but also reduce the number of taps, which reduces power consumption [15,16,17]. Due to the inherent drawbacks of linear equalizers, it is necessary to follow a half-rate decision feedback equalizer.

Fig. 1.

A typical equalization architecture with CTLE and Half-rate DFE

Due to the change of the environment, the different backplane materials and the change of the data rate, the improvement of the adaptive ability of CTLE is absolutely necessary. For the adaption CTLE based on spectrum balancing method, the power detector consumes large power. In order to solve these problems, the adaptive CTLE based on slope detection is presented in this paper, as shown in Fig. 2. The signal transmitted through the channel is first sent to a linear equalizer which has two paths: high-pass path and all-pass path. The high-pass path is used to compensate the high-frequency loss by high-frequency peaking, and the all-path is employed to adjust the low-frequency gain. The optimum proportion of high frequency and low frequency is adjusted by feedback control voltage V _ctrl. The output of the linear equalizer is adopted to produce a fixed swing and slope signal by the slicer. Slope detector &integrator are used for detecting the slope (energy)deviation between the slicer input and its output.

Fig. 2.

Adaptive CTLE

Figure 3 shows a simplified structure of half-rate DFE, which is composed of odd path and even path. Each path consists of an adder and two Flip-Flops. The rate of clock signal for odd path data and even path data is half of input data, which is illustrated by Fig. 4. The multiplexer restores half-rate data to full-speed data. The advantages of half-rate structure can be described as follows: firstly, the time constraint of the half-rate DFE is the same as the full-rate DFE, but the data duration of half-rate DFE is doubled, so it is easier for the adder to complete the operation accurately. Secondly, the architecture of half-rate DFE can reduce design difficulty of the CDR circuit and clock buffer.

Fig. 3.

Half-rate DFE

Fig. 4.

Timing diagram of half-rate DFE

3 Circuit Design

3.1 Linear Equalizer

Linear equalizer is mainly used to compensate the loss caused by channel bandwidth degradation. The design of linear equalizer must consider two issues: (1) bandwidth, which determines the range of frequency compensation; (2) boost factor, which is determined by the loss of the channel [17]. The linear equalizer shown in Fig. 5 employs a high-path and an all-path path to compensate the loss of the channel. The bandwidth of high-path is completed by the inductance peaking technique and the bandwidth of the all-path is expanded by pole zero cancellation. The ratio of high frequency and low frequency is determined by the bias voltage of the tail transistor. In other words, the adaptation of the linear equalizer is performed by the feedback control voltage V _ctrl, which is produced by the slope detector and integrator. Figure 6 shows the frequency response curve of the linear equalizer with different V _ctrl.

Fig. 5.

Linear equalizer

Fig. 6.

Frequency response of linear equalizer with different V _ctrl

3.2 Slope Detector and Integrator

Figure 7 shows the slope detector & integrator. Two coupled difference pairs, M₁ and M₂, M₃ and M₄, are used to detect the energy of the slicer input and output, respectively. The total current flowing through the coupled differential pair M₁ and M₂ can be expressed as follows:

Fig. 7.

Slope detector and integrator

$$ I_{{{\text{out}}1}} = I_{{{\text{ds}}1}} + I_{{{\text{ds}}2}} = \frac{{\mu_{\text{n}} C_{\text{ox}} }}{2}\left( {\frac{W}{L}} \right)\left( {2\left( {V_{{{\text{in}},{\text{cm}}}} - V_{\text{in}} } \right)^{2} + \frac{{V_{{{\text{in}},{\text{dm}}}}^{2} }}{2}} \right) $$

(1)

where the I _ds1 and I _ds2 are the drain current of transistor M1 and M2, respectively. V _in,com is the common mode input voltage and V _in,dm is the differential mode input voltage. The square term in the formula shows that the energy of different slope signal waveforms can be measured by I _out1. In Fig. 7, M₆ and M₇ are active load transistor, M₅ and M₆ are mirror current source, similarly, M₇ and M₈ are mirror current source. Therefore, the feedback control voltage generated by the integrator can be described as follows:

$$ V_{\text{ctrl}} = I_{\text{out2}} R_{\text{L}} - I_{\text{out1}} R_{\text{L}} = \frac{{\mu_{\text{n}} C_{\text{ox}} }}{4}\left( {\frac{W}{L}} \right)\left( {V_{{{\text{in}}2}}^{2} - V_{{{\text{in}}1}}^{2} } \right)R_{\text{L}} $$

(2)

According to Eq. (2), V _ctrl is closely related with the difference of slicer both ends signal energy. The V _ctrl feeding back to the linear equalizer adjusts the frequency response of the linear equalizer.

3.3 Slicer

Slicer implemented by two cascaded current mode logic (CML) structure is shown in Fig. 8. The slicer is a limiting amplifier so that it processes the edge and amplitude of the input signal and produces fixed swing and slope signal for the feedback loop. The slicer is a high resolution comparator. The edge of the input signal is processed into an approximate ideal binary signal, so that the slope of the slicer output is almost independent of the slope of the equalizer output signal.

Fig. 8.

Slicer

3.4 SCFL Based Latch

The sensitivity of latch has a great influence on the performance of DFE. The D Flip-Flop consists of two stages latches. Each stage latch contains three pairs of transistors, as shown in Fig. 9. Q₁ and Q₂ are input clock transistors, Q₃ and Q₄ consist of sampled transistors, Q₅ and Q₆ are latch transistors. When the CK _p/CK _n is high/low, the Q₁ is turned on and the Q₂ is turned off, the current I _ss flows through the Q₁, and the data is sampled. When CK _p/CK _n is low/high level, the output signal is latched by the latch transistor, the data remains intact.

Fig. 9.

SCFL based Latch

For latch, firstly, the size of clock signal must be large enough to ensure that the Q₁ or Q₂ can be turned off completely. Secondly, the performance of the latch is determined by the proportional relation between the latch transistor and the sampling transistor. Considering the operating speed, data retention capability and bandwidth, the proportional relation adopted in this design is 0.8.

3.5 Summer

The summer based on CML is shown in Fig. 10. The input signal V _in and its feedback signal are summed up in the form of current, and then converted into the output voltage V _out. The V _out can be expressed as follows:

Fig. 10.

Summer

$$ V_{\text{out}} = \left[ {G_{0} V_{\text{in}} (t) - G_{1} V_{\text{in}} (t - T) - G_{2} V_{\text{in}} (t - 2T)} \right]R_{L} = \left[ {C_{0} - C_{1} - C_{2} } \right]I_{SS} R_{L} $$

(3)

where G _i (i = 0, 1, 2) are the input trans conductance, C _i (i = 0, 1, 2) are the tap coefficients. In order to effectively eliminate the post-cursor and achieve a good equalization effect, it is important to select the appropriate tap coefficients C _i (i = 1, 2). Typically, it can be obtained by the impulse response of the channel or the adaptive least mean square (LMS) algorithm.

3.6 Multiplexer

Figure 11 shows the architecture of multiplexer. The 2:1 multiplexer based on SCFL is mainly composed of two cross coupled differential pair transistor. This circuit is driven by half-rate clock, which is same as the master slave flip-flop. The half-rate data can be recovered to full rate data through this circuit. When the CK _p is high, the odd path is selected. When the CK _n is high, the even path is selected. In order to improve the stability of current source, the gate length of the tail current transistor should be larger.

Fig. 11.

Multiplexer

3.7 Buffer

To drive external 50 ohms load resistance, the buffer based on CML logic was implemented in this work, as shown in Fig. 12. It is composed of multi-stage CML logic. It has the advantage of simple structure and enough bandwidth. In order to improve the driving ability, this paper adopts 3 stages. The size of tail current transistor and difference input transistor should be gradually increased, and the size of load resistance should be reduced gradually.

Fig. 12.

Buffer

4 Layout and Post Simulation

Figure 13 shows the layout of the proposed equalizer including adaptive CTLE and half-rate DFE. The total area including pads and chip guarding is 0.72 × 0.86 mm². The circuit has been submitted for fabrication. Figure 14 shows the simulation results of feedback control voltage V _ctrl+ and V _ctrl−. It can be seen that the feedback control voltage can be stable after 5 ns.

Fig. 13.

Layout of the proposed equalizer

Fig. 14.

Simulation results of feedback control voltage (V _ctrl+ and V _ctrl−)

Figure 15(a) gives the input eye diagram. The output eye diagram of adaptive CTLE and half-rate DFE are given in Fig. 15(b) and (c), respectively. It is can be seen that the eye opening is less than 0.6UI after adaptive CTLE equalization, and the eye opening can be further widened by half-rate DFE at the rate of 20 Gb/s.

Fig. 15.

Simulation results of 20 Gb/s

5 Conclusions and Future Work

In this brief, in order to deal with higher channel loss, a half-rate DFE combined with an analog adaptive CTLE based on slope detection is employed at the receiver. The adaptive CTLE can adjusts the range of high-frequency peaking and compensate the channel loss. It can effectively reduce the burden of DFE and cut down the number of taps. Eye opening is up to 0.9 UI after the CTLE and half-rate DFE equalization at 20 Gb/s. It improves that the half-rate DFE can further improve the signal integrity of serial link at the rate of 20 Gb/s.

In future work, on the one hand, because the ISI is mainly caused by the post-cursor, we will focus on the adaption performance of DFE. On the other hand, when the loss of the link reaches up to 35 dB attenuation at Nyquist frequency at 25 Gb/s or above, higher order modulation mode (such as PAM4), or other modulation methods (such as ENRZ) should be deeply studied.