Abstract
While hardware implementations allow the production of highly efficient and performance-oriented designs, exploiting features such as parallelization, their longer time to code and implement often bottlenecks rapid prototy**. On the other hand, high-level synthesis (HLS) tools allow for faster experimentation of software code to a hardware platform while demonstrating a reasonable extrapolation of the expected hardware behavior. In this work, we attempt to show a rapid prototy** of the well known HQC algorithm, using HLS, and show how with a modification of certain parameters, varying degrees of comparable results can be obtained. These results, in turn, could be used as a guide for HDL (Hardware Description Language)-RTL (Register-transfer Level) developers to enhance their designs and better prototy** time in the future. Additionally, we also demonstrate that it is possible to benefit from HQC’s versatility; by achieving a low hardware footprint whilst also maintaining good performances, even on low-cost FPGA devices, which we demonstrate on the well-known Artix-7 xc7a100t-ftg256-1.
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Notes
- 1.
We note here that compared to FPGAs, ASICs have a much higher and longer tun-around time.
- 2.
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Aguilar-Melchor, C. et al. (2023). Towards Automating Cryptographic Hardware Implementations: A Case Study of HQC. In: Deneuville, JC. (eds) Code-Based Cryptography. CBCrypto 2022. Lecture Notes in Computer Science, vol 13839. Springer, Cham. https://doi.org/10.1007/978-3-031-29689-5_4
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