Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform

Abstract

CNN (convolutional neural networks) have achieved great success in learning features from Euclidean-structured data. While lots of learning tasks require dealing with graph data. In these application scenarios where CNN cannot operate, GCN (graph neural networks) have shown appealing performance and increasing attention in recent years. However, according to our research, the computational complexity and storage overhead of the network also increase, making it a challenge to accelerate on a single FPGA. Accordingly, in this work, we focus on accelerating a deep GCN (DAGCN) on a CPU-multi FPGA platform by proposing a deep-pipelined acceleration scheme. To fully explore the parallelism that exists in DAGCN, we propose a graph convolutional neural accelerator (GCNAR) characterized by integration of a multiple 1-D systolic array. In addition, we also adopt an existing CSR algorithm-based partitioning scheme for large-scale matrix-vector multiplication in the design of our GCNAR, which effectively improves the computational efficiency of GCNAR. Moreover, we develop performance and resource evaluation models to help us determine the optimal design parameters for maximizing the accelerator throughput. Evaluation on real-world graph datasets demonstrates that our FPGA-based solution can achieve comparable performance to state-of-the-art GCN accelerations. In addition, compared to CPU and GPU solutions, our accelerator can achieve 196 times and 115 times the improvement for graph classification respectively in terms of processing latency.

Supported by Supported by organization National Natural Science Foundation of China (NSFC) project 61802420 and National Program on Key Basic Research Project 2016YFB1000401 and 2016YFB1000403.