Abstract
We discuss map** the matrix multiplication algorithm onto a two-level hierarchical memory system which incorporates DMA capabilities between levels, as available on Digital Signal Processors (DSPs). We show that it is possible to hide the hierarchical nature of the memory system from the processor, so that computations can proceed at the processor’s speed. This is accomplished by the use of a block algorithm, and by prefetching data from the slower second-level memory into the faster but smaller first-level memory under DMA control. The Texas Instruments TMS 320C30 Digital Signal Processor is used as an example, and performance estimates for different memory timings are given. These results are also compared to the performance of executing the matrix multiplication algorithm without exploiting the DMA capabilities.
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© 1992 Springer Science+Business Media New York
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Palacios, I., Medina, M., Moreno, J. (1992). Matrix Multiplication on Digital Signal Processors and Hierarchical Memory Systems. In: Baeza-Yates, R., Manber, U. (eds) Computer Science. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3422-8_39
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DOI: https://doi.org/10.1007/978-1-4615-3422-8_39
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6513-6
Online ISBN: 978-1-4615-3422-8
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