Abstract
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel and distributed execution. Fine-grain scheduling decisions are made at compile time, and coarse-grain scheduling decisions are made at run time. The approach consists of two components: compiler technology which performs the static analysis (thread extraction), and an architecture which takes over the responsibility for scheduling and distributing the threads. Each processor is augmented with a broker, whose responsibility it is to shop for tasks for the processor to perform. This approach aims to provide an adaptive run-time distribution of computation for irregular problems such as the simulation of embedded systems. Finally, this approach is general enough to allow the seamless incorporation of heterogeneous hardware, in particular including dynamically reconfigurable hardware, e.g. FPGAs.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Annavaram, Murali and Najjar, Walid (1996), Comparison of Two Storage Models in Data-Driven Multithreaded Architectures,Eighth IEEE Symposium on Parallel and Distributed Processing (SPDP), New Orleans, LA., Oct. 1996, IEEE Computer Society Press, 122–129.
Brebner, Gordon (1998), Field-Programmable Logic: Catalyst for New Computing Paradigms,Proc. 81h International Workshop on Field-Programmable Logic and Applications (FPLA ‘88), Springer Verlag.
Culler, David E., Goldstein, Seth Copen, Schauser, Klaus Erik and von Eicken, Thorsten (1993) TAM - A Compiler Controlled Threaded Abstract Machine, Journal of Parallel and Distributed Computing, Special Issue on Dataflow, June, 1993.
Ditze, Carsten (1995), DReaMS - Concepts of a distributed real-time management system, Proc. 1995 IFIP/IFAC Workshop on Real-Time Programming.
Grewe, Claus, Obelöer, Wolfgang and Pals, Holger (1998), Kombination von anwendungs-und systemintegrierter Lastverwaltung mit Mobilen Agenten, Proc. 17. PARS Workshop, Karlsruhe, 16.-17. September, PARS Mitteilungen Nr. 17, 98–107.
Hagersten, E., Landin, A. and Haridi, S. (1992), DDM - A Cache-Only Memory Architecture,IEEE Computer, 25(9), 44–54.
Haridi, Seif and Hagersten, Erik (1989), The Cache Coherence Protocol of the Data Diffusion Machine,Proceedings of the PARLE 89, Vol. 1, Springer-Verlag, 1–18.
Klang, Melanie (1997), Hierarchische Zerlegung von Datenflußgraphen für mehrfädige Architekturen, Diplomarbeit, Fachbereich Informatik, J. W. Goethe-Universität, Oct. 1997.
Kleinjohann, Bernd, Tacken, Jürgen, and Tahedl, Christoph (1997), A Design Environment Using High-Level Petri-Nets as Common Model for Specification, Analysis, and Validation of Hybrid Real-Time Systems, 3. ITG/GI/GMM Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen, Holzau (Germany), Febuary 1997.
Moore, Ronald, Zickenheiner, Stefan, Klauer, Bernd, Henritzi, Frank, Bleck, Andreas, and Waldschmidt, Klaus (1996), Neural Compiler Technology for a Parallel Architecture, International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA ‘86), Sunnyvale, CA, Aug. 1996.
Moore, Ronald, Klauer, Bernd and Waldschmidt, Klaus (1997), Compiler Technology for Two Novel Computer Architectures, 14th ITG/GI-Fachtagung Architektur von Rechensystemen (ARCHS ‘87), Rostock, Germany, Sept. 1997.
Moore, Ronald, Klauer, Bernd and Waldschmidt, Klaus (1998a), A Combined Virtual Shared Memory and Network which Schedules, International Journal of Parallel and Distributed Systems and Networks, 1(2), 51–56, 1998. Originally appeared at the International Conference on Parallel and Distributed Systems (Euro-PDS ‘87), Barcelona, June, 1997.
Moore, Ronald, Klauer, Bernd and Waldschmidt, Klaus (1998b), Automatic Scheduling for Cache Only Memory Architectures, Third International Conference on Massively Parallel Computing Systems (MPCS ‘88), Boulder, Colorado, April, 1998.
Nikhil, Rishiyur S. (1993), A Multithreaded Implementation of Id using P-RISC Graphs, Proceedings of the Sixth Annual Workshop on Languages and Compilers for Parallel Computing, Portland, Oregon, Aug. 1993, Springer Verlag LNCS 768, 390–405.
Page, Ian (1998), Design of Future Systems,Proc. Design Automation and Test Europe (DATE `98), IEEE Press, 343–347.
Patterson, David A. (1997), Microprocessors in 2020,Scientific American Special Issue: The Solid-State Century, 8(1), 86–88.
Saulsbury, Ashley, Wilkinson, Tim, Carter, John and Landin, Anders (1996), An Argument For Simple COMA, First IEEE Symposium on High Performance Computer Architecture, Rayleigh, North Carolina 276–285.
Villasenor, John and Mangione-Smith, William H. (1997), Configurable Computing, Scientific American, June, 1997.
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer Science+Business Media New York
About this chapter
Cite this chapter
Moore, R., Klang, M., Klauer, B., Waldschmidt, K. (1999). Combining Static Partitioning with Dynamic Distribution of Threads. In: Rammig, F.J. (eds) Distributed and Parallel Embedded Systems. DIPES 1998. IFIP — The International Federation for Information Processing, vol 25. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35570-2_7
Download citation
DOI: https://doi.org/10.1007/978-0-387-35570-2_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-5006-5
Online ISBN: 978-0-387-35570-2
eBook Packages: Springer Book Archive