Abstract
This article describes the architecture and the design of a high speed packet-switched communication network for multi-processor systems. It consists of a autonomous communication layer connected to a computational layer. The proposed network architecture uses a store and forward communication mechanism to maximally share resources. Each node in the network dynamically forwards messages between a source and a destination using the adaptive bounding box algorithm. In combination with a small message size and parallel datapaths the routing speed is maximized. The network uses minimum sized message queues and dynamically avoids blocked communication links in order to reduce the communication delay. Manufacturing constraints of present planar VLSI technology favours a regular locally connected network topology, e.g. a mesh. A custom VLSI prototype of the communication processor for the network architecture demonstrates the feasibility of the basic architecture.
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S. Ahuja, N.J. Carriero, D. Gelernter, V. Krishnaswamy, “Matching Language and Hardware for Parallel Computation in Linda”, IEEE Transactions on Computers, Vol. 37, No 8, 1988
Paul Anderson, Chris Hanking, Paul Kelly, Peter Osmon, Malcolm Shute, “COBWEB-2: Structured Specification of a Wafer-Scale Supercomputer”, Proc. PARLE, 1987
J.K. Annot, R.A.H. van Twist, “A Novel Deadlock Free and Starvation Free Packet Switching Communication Processor”, Proc. PARLE, 1987
William J. Dally, “A VLSI Architecture for Concurrent Data Structures”, Thesis, March 1986
William J. Dally, Charles L. Seitz, “The torus routing chip”, Distributed Computing, Vol. 1, page 187–196, 1986
Albert G. Greenberg, Jonathan Goodman, “Sharp Approximate Models of Adaptive Routing in Mesh Networks”, Proc. Teletraffic and Performance Evaluation, 1986
Klaus D. Günther, “Prevention of Deadlocks in Packet-Switched Data Transport Systems”, IEEE Transactions on Communications, Vol 29, No. 4, April 1981
Al Kernek, “Massively Parallel Systems — The Revolution has begun”, SuperComputing Magazine, page 25–27, Fall 1988
S. Lucco, “A heuristic Linda Kernel for Hypercube Multiprocessors”, Proc. 1986 Workshop Hypercube Multiprocessors, 1986
N. F. Maxemchuk, “Regular Mesh Topologies in Local and Metropolitan Area Networks”, AT&T Technical Journal, Vol. 64, No. 7, Sept. 1985
David May, “OCCAM implementation on the Transputer”, Proc. of the 12th Symposium on Computer Architecture, 1985
D. Parkinson, “Organizational aspects of using parallel computers”, Parallel Computing, Vol. 5, page 75–83, 1987
A.G. Starreveld, W.G.P. Mooij, W.E. van Waning, L.O. Hertzberger, “Design and Evaluation of a Parallel Implementation of Prolog”, Parallel Processing and Applications, page 355–362, 1988
W. Vree, “Experiments with coarse grain parallel graph reduction”, Workshop on Parallel Computing of the FGCS congress, 1987
N.H.E. Weste, “MULGA — An Interactive Symbolic Layout System for the Design of Integrated Circuits”, The Bell System Technical Journal, Vol. 60, No. 6, page 823–857, July-August 1981
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© 1989 Springer-Verlag Berlin Heidelberg
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Mooij, W.G.P., Ligtenberg, A. (1989). Architecture of a communication network processor. In: Odijk, E., Rem, M., Syre, JC. (eds) PARLE '89 Parallel Architectures and Languages Europe. PARLE 1989. Lecture Notes in Computer Science, vol 365. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540512845_43
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DOI: https://doi.org/10.1007/3540512845_43
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