Abstract
In this paper, we propose to decouple the recovery mechanism for data speculation from dynamic instruction scheduling structure. Instruction reissue mechanism for data speculation has a serious impact on processor performance. The effective capacity of instruction window is reduced since instructions dependent upon a speculated instruction must remain in instruction window until they are committed. The decoupling of the recovery and scheduling mechanisms solves the problem. A small instruction window schedules instructions and its entry is released immediately when an instruction is dispatched. A large instruction buffer is active only when a misspeculation occurs and is used to reissue instructions dependent upon the misspeculated instruction. Using a cycle-by-cycle simulator, we evaluated the proposal and found that the decoupling is useful.
Chapter PDF
Keywords
- Data Prediction
- Processor Performance
- Instruction Level Parallelism
- Branch Predictor
- Superscalar Processor
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Akkary, H., Driscoll, M.A.: A dynamic multithreading processor. 31st Int’l Symp. on Microarchitecture (1998)
Burger, D., Austin, T.M.: The SimpleScalar tool set, version 2.0. ACM SIGARCH Computer Architecture News, 25(3) (1997)
Chrysos, G.Z., Emer, J.S.: Memory dependence prediction using store sets. 25th Int’l Symp. on Computer Architecture (1998)
Gabbay, F.: Speculative execution based on value prediction. Technical Report #1080, Dept. of Electrical Eng., Technion (1996)
Lipasti, M.H., Wilkerson, C.B., Shen, J.P.: Value locality and load value prediction. Int’l Conf. on Architectural Support for Programming Languages and Operation Systems VII (1996)
Palacharla, S., Jouppi, N.P., Smith, J.E: Complexity-effective superscalar processors. 24th Int’l Symp. on Computer Architecture (1997)
Rotenberg, E., Jacobson, Q., Sazeidas, Y., Smith, J.: Trace processors. 30th Int’l Symp. on Microarchitecture (1997)
Sato, T.: Data dependence speculation using data address prediction and its enhancement with instruction reissue. Euromicro’ 98 Conf., Workshop on Digital System Design (1998).
Sohi, G.S.: Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Trans. Comput., 39(3) (1990)
Tyson, G. Austin, T.M.: Improving the accuracy and performance of memory communication through renaming. 30th Int’l Symp. on Microarchitecture (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Sato, T. (1999). Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure. In: Amestoy, P., et al. Euro-Par’99 Parallel Processing. Euro-Par 1999. Lecture Notes in Computer Science, vol 1685. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48311-X_182
Download citation
DOI: https://doi.org/10.1007/3-540-48311-X_182
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66443-7
Online ISBN: 978-3-540-48311-3
eBook Packages: Springer Book Archive