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Complete depletion area in SOI junctionless FETs by multiple buried P-type pockets

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Abstract

This paper describes a unique approach for calculating the complete depletion area in silicon-on-insulator (SOI) junctionless FETs (JL-FET). The suggested approach significantly reduces the OFF-current (IOFF) by utilizing several P-type pockets at the channel's bottom. Using calibrated simulations, the recommended device exhibits a substantial ION/IOFF ratio of 5 × 105, decreased DIBL and subthreshold slope, and an accurate ON-current (ION) value at accumulation modes. By using our approach and generating a larger depletion area, we reduce the gate capacitance (CG) and the gate–drain capacitance (CGD). The suggested structure's electrical properties exhibit encouraging results compared to a conventional device, and DC and RF effects have been explored.

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Data Availability Statement

This manuscript has associated data in a data repository. [Authors’ comment: The data that support the findings of this study are available from the authors upon reasonable request.]

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The authors received no financial support for the research, authorship and/or publication of this article.

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Authors and Affiliations

  1. Electrical Engineering Department, Semnan University, Semnan, Iran

    Mohammad Bolokian, Ali A. Orouji, Abdollah Abbasi & Ramin Noribayat

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  1. Mohammad Bolokian
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  2. Ali A. Orouji
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  3. Abdollah Abbasi
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  4. Ramin Noribayat
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Contributions

MB contributed to conceptualization, writing—original draft, and software. AAO performed supervision and review and editing. AA contributed to review and editing, and software. RN performed writing—original draft.

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Correspondence to Ali A. Orouji.

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Bolokian, M., Orouji, A.A., Abbasi, A. et al. Complete depletion area in SOI junctionless FETs by multiple buried P-type pockets. Eur. Phys. J. Plus 138, 527 (2023). https://doi.org/10.1140/epjp/s13360-023-04147-2

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