SpringerLink
Log in

Modeling and Characterization of the 3rd Order Charge-Pump PLL: a Fully Event-driven Approach

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, the event-driven concept is applied to the third order Charge-Pump Phase-Locked Loop (CP-PLL) and leads to the description of a behavioral model based on a set of exact and non-linear recursive equations. A simulator (SIMPLL), written in C and using this model, checks the conventional z-domain approximate stability theory and brings to the fore the strongly non-linear nature of the CP-PLL that a careful and safe design must take into account. Thus, in order to have a more exhaustive design characterization, a statistical analysis method is explored.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
EUR 32.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or Ebook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Germany)

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. C. D. Hedayat, A. Hachem, Y. Leduc, and Gérard Benbassat, “High-level modeling applied to the second order Charge-Pump PLL circuit.” Texas Instruments Technical Journal 14, pp. 99-108, 1997.

    Google Scholar 

  2. Mark van Paemel, “Analysis of a Charge-Pump PLL: A New Model.” IEEE Trans. Commun. 42(7), pp. 2490-2498, 1994.

    Google Scholar 

  3. F. M. Gardner, “Charge-Pump Phase-Lock Loops.” IEEE Trans. Commun. COM-28(11), pp. 1849-1858, 1980.

    Google Scholar 

  4. Patrick Siniscalchi, “Design and Analysis of Programmable On-Chip Frequency Synthesizers.” Texas Instruments Technical Journal 11, pp. 64-73, 1994.

    Google Scholar 

  5. A. Demir, E. Liu, A. Sangiovanni-Vincentelli, and I. Vassiliou, “Behavioral Simulation Techniques for Phase/Delay-Locked Systems.” In Proc. Custom Integrated Circuit Conference, pp. 453-456, San Diego, 1994.

  6. Edward Liu and Alberto L. Sangiovanni-Vincentelli, “Behavrioral Representations for VCO and Detectors.” IEEE Custom Integrated Circuits Conference, 1992.

  7. B. A. Antao, F. M. El-Turky, and R. Leonowich, “Behavioral Modeling Phase-locked Loops for Mixed-Mode Simulation.” Analog Integrated Circuits and Signal Processing 10, pp. 45-65, 1996.

    Google Scholar 

  8. R. E. Best, “Phase Locked Loops, Theory, Design and Applications.” McGraw Hill, 1983.

  9. H. Meyr and G. Ascheid, “Synchronization in Digital Communications, Volume 1, Phase-, Frequency-Locked Loops and Amplitude Control.” John Wiley & Sons Inc, 1990.

Download references

Author information

Authors and Affiliations

  1. Laboratoire de Physique Electronique des Solides, Universite´ de Nice-Sophia Antipolis, Parc Valrose, 06108, NICE Ce´dex 2, France

    Christian D. Hedayat & Ahmed Hachem

  2. Texas Instruments, France-B.P. 5, 06271, Villeneuve Loubet Ce´dex, France

    Yves Leduc & Ge´rard Benbassat

Authors
  1. Christian D. Hedayat
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ahmed Hachem
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yves Leduc
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Ge´rard Benbassat
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hedayat, C.D., Hachem, A., Leduc, Y. et al. Modeling and Characterization of the 3rd Order Charge-Pump PLL: a Fully Event-driven Approach. Analog Integrated Circuits and Signal Processing 19, 25–45 (1999). https://doi.org/10.1023/A:1008326315191

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008326315191

Search

Navigation