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Electronics Hardware Chip Design for Router–Router Communication

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Proceedings of the National Academy of Sciences, India Section A: Physical Sciences Aims and scope Submit manuscript

Abstract

In contrast to scalar CPUs, end scaling refers to the use of heterogeneous multiprocessor systems-on-chip. Calculations made by an application consume less energy when it is run on the appropriate processor elements (PEs) that have been enhanced for difficult operations. However, as the PEs are increased, communication becomes more and more important. The on-chip interconnect technology of NoC uses scaled-down communication techniques from networks. A router is a physical or virtual device that acts as a shared form of gateway for material between two or more packet-switched processor networks. The router is used for NoC connection in SoC and concerned designs for router–router communication. This paper presents the hardware chip design of the 2D routers and employs router–router chip communication between two routers using independent chips and integrated NoC. The router hardware chip design is done in **linx Integrated System Environment (ISE) 14.7 software. Modelsim 10.0 is used for logic verification utilizing data packets sent from all input/output ports.

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Acknowledgements

We are thankful to the Faculty of Engineering and Technology, Gurukula Kangri (Deemed to be University), Haridwar, India, for hardware support and the University of Petroleum and Energy Studies, Dehradun, India, VLSI Lab, to provide support to carry out the simulation work.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, Gurukula Kangri (Deemed to Be University), Haridwar, India

    Prateek Agarwal & Tanuj Kumar Garg

  2. Department of Electrical and Electronics Engineering, School of Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India

    Adesh Kumar

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  1. Prateek Agarwal
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  2. Tanuj Kumar Garg
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  3. Adesh Kumar
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Correspondence to Prateek Agarwal.

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Agarwal, P., Garg, T.K. & Kumar, A. Electronics Hardware Chip Design for Router–Router Communication. Proc. Natl. Acad. Sci., India, Sect. A Phys. Sci. 93, 703–710 (2023). https://doi.org/10.1007/s40010-023-00853-9

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