Abstract
A highly configurable fast Fourier transform intellectual property core (FFT IP core) that can be mounted on Avalon bus of Nios II processor is designed in this paper, by the means of custom-built components in SOPC Builder. Not only the data number can be configured to 2n and the data width can be configured as integer or floating-point number of 32 bits, but also the number of inner butterfly units is configurable, which can effectively resolve the contradiction between speed and hardware resource occupancy. The IP core is designed by butterfly computing elements of a mixed radix-4 and radix-2 algorithm and applies the in-place addressing scheme and reusing method to reduce hardware resources consumption. Functional simulation by Quartus II platform proves that the results calculated by FFT IP core are accordant with the Matlab results. Hardware test on DE2 development board by timestamp timer demonstrates that the FFT IP core costs only 34.8 μs to achieve FFT of 512 sampled data with precision of 32-bit floating point. It is demonstrated that the IP core has the advantages of feasible configuration, easy use, and high precision.
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Foundation item: Supported by the Natural Science Foundation of Hubei Province (2011CDC017)
Biography: LIU Sanjun, male, Ph.D. candidate, research direction: information theory, multiuser communications, embedded system and SOPC technology.
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Liu, S., Sun, L., Li, S. et al. Highly configurable floating-point FFT IP Core with reusing method. Wuhan Univ. J. Nat. Sci. 18, 59–66 (2013). https://doi.org/10.1007/s11859-013-0894-z
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DOI: https://doi.org/10.1007/s11859-013-0894-z