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Single-event effect hardening of the Schottky contact super barrier rectifier (SSBR) with high-k gate dielectric

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Abstract

In this paper, the single-event effects of Schottky contact super barrier rectifier (SSBR) and conventional super barrier rectifier (SBR) as comparison structure are simulated and discussed. The high-k dielectric has a larger dielectric constant and a larger physical thickness at the same equivalent oxide thickness (EOT). Therefore, it is used to enhance the single-event gate rupture (SEGR) performance of the devices. Simulation results show that the SEGR performance of SSBR and SBR is significantly improved after using high-k dielectric as the gate dielectric. Furthermore, due to the absence of a parasitic bipolar junction transistor (BJT), SSBR has a higher single-event burnout (SEB) performance than conventional SBR. In conclusion, SSBR has a good performance of single-event effect (SEGR and SEB) and is better than that of SBR after using high-k dielectric as the gate dielectric.

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References

  1. Chen, W., Liao, R., Zeng, Z., Zhang, P.: A novel Schottky contact super barrier rectifier with a top N-enhancement layer and a P-injector. J Comput Electron 17, 707–712 (2018). https://doi.org/10.1007/s10825-018-1128-6

    Article  Google Scholar 

  2. Chen, W., Liao, R., Zeng, Z., Zhang, P., Zhong, Y., Tan, K., Chen, H., Zhang, B.: Analyses and experiments of the schottky contact super barrier rectifier (SSBR). IEEE Electron Device Lett. 38, 902–905 (2017). https://doi.org/10.1109/LED.2017.2703597

    Article  Google Scholar 

  3. Rodov, V., Ankoudinov, A.L., Taufik, Super barrier rectifier—a new generation of power diode. IEEE Trans. on Ind. Applicat. 44, 234–237 (2008). https://doi.org/10.1109/TIA.2007.912752

    Article  Google Scholar 

  4. Rodov, V., Ankudinov, A.L., Ghosh, P.: High injection regime of the super barrier™ rectifier. Solid-State Electron. 51, 714–718 (2007). https://doi.org/10.1016/j.sse.2007.03.006

    Article  Google Scholar 

  5. Won, J.I., Park, K.S., Cho, D.H., Koo, J.G., Kim, S.G., Lee, J.H.: Diode and MOSFET properties of trench-gate-type super-barrier rectifier with P-body implantation condition for power system application. ETRI J 38, 244–251 (2016). https://doi.org/10.4218/etrij.16.2515.0024

    Article  Google Scholar 

  6. Titus, J.L., Wheatley, C.F.: Experimental studies of single-event gate rupture and burnout in vertical power MOSFETs. IEEE Trans. Nucl. Sci. 43, 533–545 (1996). https://doi.org/10.1109/23.490899

    Article  Google Scholar 

  7. Wang, Y., Yu, C.-H., Li, X.-J., Yang, J.-Q.: A comparative study on heavy-ion irradiation impact on p-channel and n-channel power UMOSFETs. IEEE Trans. Nucl. Sci. 69, 1249–1256 (2022). https://doi.org/10.1109/TNS.2022.3175954

    Article  Google Scholar 

  8. Allenspach, M., Dachs, C., Johnson, G.H., Schrimpf, R.D., Lorfevre, E., Palau, J.M., Brews, J.R., Galloway, K.F., Titus, J.L., Wheatley, C.F.: SEGR and SEB in n-channel power MOSFETs. IEEE Trans. Nucl. Sci. 43, 2927–2931 (1996). https://doi.org/10.1109/23.556887

    Article  Google Scholar 

  9. Titus, J.L.: An updated perspective of single event gate rupture and single event burnout in power MOSFETs. IEEE Trans. Nucl. Sci. 60, 1912–1928 (2013). https://doi.org/10.1109/TNS.2013.2252194

    Article  Google Scholar 

  10. Brews, J.R., Allenspach, M., Schrimpf, R.D., Galloway, K.F., Titus, J.L., Wheatley, C.F.: A conceptual model of a single-event gate-rupture in power MOSFETs. IEEE Trans. Nucl. Sci. 40, 1959–1966 (1993). https://doi.org/10.1109/23.273457

    Article  Google Scholar 

  11. Allenspach, M., Mouret, I., Titus, J.L., Wheatley, C.F., Pease, R.L., Brews, J.R., Schrimpf, R.D., Galloway, K.F.: Single-event gate-rupture in power MOSFETs: prediction of breakdown biases and evaluation of oxide thickness dependence. IEEE Trans. Nucl. Sci. 42, 1922–1927 (1995). https://doi.org/10.1109/23.489234

    Article  Google Scholar 

  12. Wheatley, C.F., Titus, J.L., Burton, D.I.: Single-event gate rupture in vertical power MOSFETs; an original empirical expression. IEEE Trans. Nucl. Sci. 41, 2152–2159 (1994). https://doi.org/10.1109/23.340556

    Article  Google Scholar 

  13. Muthuseenu, K., Barnaby, H.J., Galloway, K.F., Koziukov, A.E., Maksimenko, T.A., Vyrostkov, M.Y., Bu-Khasan, K.B., Kalashnikova, A.A., Privat, A.: Analysis of SEGR in silicon planar gate super-junction power MOSFETs. IEEE Trans. Nucl. Sci. 68, 611–616 (2021). https://doi.org/10.1109/TNS.2021.3053168

    Article  Google Scholar 

  14. Muthuseenu, K., Barnaby, H.J., Galloway, K.F., Koziukov, A.E., Maksimenko, T.A., Vyrostkov, M.Y., Bu-Khasan, K.B., Kalashnikova, A.A., Privat, A.: Single-event gate rupture hardened structure for high-voltage super-junction power MOSFETs. IEEE Trans. Electron Devices 68, 4004–4009 (2021). https://doi.org/10.1109/TED.2021.3091952

    Article  Google Scholar 

  15. Wan, X., Zhou, W.S., Ren, S., Liu, D.G., Xu, J., Bo, H.L., Zhang, E.X., Schrimpf, R.D., Fleetwood, D.M., Ma, T.P.: SEB hardened power MOSFETs with high-k dielectrics. IEEE Trans. Nucl. Sci. 62, 2830–2836 (2015). https://doi.org/10.1109/TNS.2015.2498145

    Article  Google Scholar 

  16. Liao, X., Liu, Y., Xu, C., Li, J., Yang, Y.: Single event burnout hardening technique for high-voltage p-i-n diodes with field limiting rings termination structure. IEEE Trans. Electron Devices 69, 675–681 (2022). https://doi.org/10.1109/TED.2021.3137135

    Article  Google Scholar 

  17. Liu, S., Titus, J.L., Boden, M.: Effect of buffer layer on single-event burnout of power DMOSFETs. IEEE Trans. Nucl. Sci. 54, 2554–2560 (2007). https://doi.org/10.1109/TNS.2007.910869

    Article  Google Scholar 

  18. Wang, Y., Zhang, Y., Cao, F., Shan, M.-G.: Single-event burnout hardened structure of power UMOSFETs with Schottky source. IEEE Trans. Power Electron. 29, 3733–3737 (2014). https://doi.org/10.1109/TPEL.2013.2280019

    Article  Google Scholar 

  19. Zhou, X., Jia, Y., Hu, D., Wu, Y.: A simulation-based comparison between Si and SiC MOSFETs on single-event burnout susceptibility. IEEE Trans. Electron Devices 66, 2551–2556 (2019). https://doi.org/10.1109/TED.2019.2908970

    Article  Google Scholar 

  20. Liao, X., Yang, Y., Liu, Y., Xu, C.: Simulation aided hardening of power diodes to prevent single event burnout. IEEE Trans. Electron Devices 69, 5088–5095 (2022). https://doi.org/10.1109/TED.2022.3191630

    Article  Google Scholar 

  21. Dachs, C., Roubaud, F., Palau, J.-M., Bruguier, G., Gasiot, J., Tastet, P.: Evidence of the ion’s impact position effect on SEB in N-channel power MOSFETs. IEEE Trans. Nucl. Sci. 41, 2167–2171 (1994). https://doi.org/10.1109/23.340558

    Article  Google Scholar 

  22. Liu, S., Boden, M., Girdhar, D.A., Titus, J.L.: Single-event burnout and avalanche characteristics of power DMOSFETs. IEEE Trans. Nucl. Sci. 53, 3379–3385 (2006). https://doi.org/10.1109/TNS.2006.884971

    Article  Google Scholar 

  23. Wang, Y., Cheng-Hao, Yu., Dou, Z., Xue, W.: Single-event burnout hardening of power UMOSFETs with integrated Schottky diode. IEEE Trans. Electron Devices 61, 1464–1469 (2014). https://doi.org/10.1109/TED.2014.2312948

    Article  Google Scholar 

  24. Verma, R., Ranjan, S., Naugarhiya, A.: Analysis of single event gate rupture in trench gate SJ-VDMOS with SiO2-Si3N4 dielectric stacking. In: 2021 IEEE region 10 symposium (TENSYMP). Presented at the 2021 IEEE Region 10 symposium (TENSYMP), IEEE, Jeju, Korea, Republic of, pp. 1–6 (2021). https://doi.org/10.1109/TENSYMP52854.2021.9550886

  25. Amjath, M., Ranjan, S., Naugarhiya, A.: SEGR analysis of super junction VDMOS using HfO 2 as gate dielectric. In: 2022 Second international conference on advances in electrical, computing, communication and sustainable technologies (ICAECT). Presented at the 2022 second international conference on advances in electrical, computing, communication and sustainable technologies (ICAECT), IEEE, Bhilai, India, pp. 1–5 (2022). https://doi.org/10.1109/ICAECT54875.2022.9808021

  26. Byoung Hun Lee, Laegu Kang, Wen-Jie Qi, Renee Nieh, Yongjoo Jeon, Katsunori Onishi, Lee, J.C.: Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application. In: International electron devices meeting 1999. Technical Digest (Cat. No.99CH36318). Presented at the international electron devices meeting 1999. Technical Digest, IEEE, Washington, DC, USA, pp. 133–136 (1999). https://doi.org/10.1109/IEDM.1999.823863

  27. Jamison, P.C., Tsunoda, T., Vo, T.A., Li, J., Jagannathan, H., Shinde, S.R., Paruchuri, V.K., Gall, D.: SiO2 free HfO2 gate dielectrics by physical vapor deposition. IEEE Trans. Electron Devices 62, 2878–2882 (2015). https://doi.org/10.1109/TED.2015.2454953

    Article  Google Scholar 

  28. Wallace, R.M., Wilk, G.D.: High-κ dielectric materials for microelectronics. Crit. Rev. Solid State Mater. Sci. 28, 231–285 (2003). https://doi.org/10.1080/714037708

    Article  Google Scholar 

  29. Reddy, P.K.V., Kotamraju, S.: Improved device characteristics obtained in 4H-SiC MOSFET using high-k dielectric stack with ultrathin SiO2-AlN as interfacial layers. Mater. Sci. Semicond. Process. 80, 24–30 (2018). https://doi.org/10.1016/j.mssp.2018.02.012

    Article  Google Scholar 

  30. Wilk, G.D., Wallace, R.M., Anthony, J.M.: High-κ gate dielectrics: current status and materials properties considerations. J. Appl. Phys. 89, 5243–5275 (2001). https://doi.org/10.1063/1.1361065

    Article  Google Scholar 

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Acknowledgements

This work was supported by Project of Chongqing Natural Science Foundation (No. cstc2020jcyj-msxmX0572), Science and Technology on Analog Integrated Circuit Laboratory Foundation Project, China (No. 6142802200510), and Project Supported by the Fundamental Research Funds for the Central Universities (No. 2020CDJ-LHZZ-076).

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Zhang, A., Chen, W., Huang, J. et al. Single-event effect hardening of the Schottky contact super barrier rectifier (SSBR) with high-k gate dielectric. J Comput Electron 22, 1463–1471 (2023). https://doi.org/10.1007/s10825-023-02088-8

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