Abstract
This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors.
With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome.
The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.
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Metra, C., Favalli, M., Olivo, P. et al. Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. J Electron Test 6, 7–22 (1995). https://doi.org/10.1007/BF00993127
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DOI: https://doi.org/10.1007/BF00993127